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NVMe: Add a pci_driver shutdown method
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/nvme.h>
20#include <linux/bio.h>
8de05535 21#include <linux/bitops.h>
b60503ba 22#include <linux/blkdev.h>
fd63e9ce 23#include <linux/delay.h>
b60503ba
MW		 24#include <linux/errno.h>
25#include <linux/fs.h>
26#include <linux/genhd.h>
5aff9382 27#include <linux/idr.h>
b60503ba
MW		 28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/kdev_t.h>
1fa6aead 32#include <linux/kthread.h>
b60503ba
MW		 33#include <linux/kernel.h>
34#include <linux/mm.h>
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/pci.h>
be7b6275 38#include <linux/poison.h>
c3bfe717 39#include <linux/ptrace.h>
b60503ba
MW		 40#include <linux/sched.h>
41#include <linux/slab.h>
42#include <linux/types.h>
5d0f6131 43#include <scsi/sg.h>
797a796a
HM		 44#include <asm-generic/io-64-nonatomic-lo-hi.h>
45
b60503ba
MW		 46#define NVME_Q_DEPTH 1024
47#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
48#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
e85248e5 49#define ADMIN_TIMEOUT (60 * HZ)
b60503ba
MW		 50
51static int nvme_major;
52module_param(nvme_major, int, 0);
53
58ffacb5
MW		 54static int use_threaded_interrupts;
55module_param(use_threaded_interrupts, int, 0);
56
1fa6aead
MW		 57static DEFINE_SPINLOCK(dev_list_lock);
58static LIST_HEAD(dev_list);
59static struct task_struct *nvme_thread;
9a6b9458 60static struct workqueue_struct *nvme_workq;
1fa6aead 61
d4b4ff8e
KB		 62static void nvme_reset_failed_dev(struct work_struct *ws);
63
4d115420
KB		 64struct async_cmd_info {
65 struct kthread_work work;
66 struct kthread_worker *worker;
67 u32 result;
68 int status;
69 void *ctx;
70};
71
b60503ba
MW		 72/*
73 * An NVM Express queue. Each device has at least two (one for admin
74 * commands and one for I/O commands).
75 */
76struct nvme_queue {
77 struct device *q_dmadev;
091b6092 78 struct nvme_dev *dev;
b60503ba
MW		 79 spinlock_t q_lock;
80 struct nvme_command *sq_cmds;
81 volatile struct nvme_completion *cqes;
82 dma_addr_t sq_dma_addr;
83 dma_addr_t cq_dma_addr;
84 wait_queue_head_t sq_full;
1fa6aead 85 wait_queue_t sq_cong_wait;
b60503ba
MW		 86 struct bio_list sq_cong;
87 u32 __iomem *q_db;
88 u16 q_depth;
89 u16 cq_vector;
90 u16 sq_head;
91 u16 sq_tail;
92 u16 cq_head;
c30341dc 93 u16 qid;
e9539f47
MW		 94 u8 cq_phase;
95 u8 cqe_seen;
22404274 96 u8 q_suspended;
4d115420 97 struct async_cmd_info cmdinfo;
b60503ba
MW		 98 unsigned long cmdid_data[];
99};
100
101/*
102 * Check we didin't inadvertently grow the command struct
103 */
104static inline void _nvme_check_size(void)
105{
106 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
107 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
108 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
109 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
110 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 111 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 112 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 113 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
114 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
115 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
116 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 117 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 118}
119
5c1281a3 120typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
c2f5b650
MW		 121 struct nvme_completion *);
122
e85248e5 123struct nvme_cmd_info {
c2f5b650
MW		 124 nvme_completion_fn fn;
125 void *ctx;
e85248e5 126 unsigned long timeout;
c30341dc 127 int aborted;
e85248e5
MW		 128};
129
130static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
131{
132 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
133}
134
22404274
KB		 135static unsigned nvme_queue_extra(int depth)
136{
137 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
138}
139
b60503ba 140/**
714a7a22
MW		 141 * alloc_cmdid() - Allocate a Command ID
142 * @nvmeq: The queue that will be used for this command
143 * @ctx: A pointer that will be passed to the handler
c2f5b650 144 * @handler: The function to call on completion
b60503ba
MW		 145 *
146 * Allocate a Command ID for a queue. The data passed in will
147 * be passed to the completion handler. This is implemented by using
148 * the bottom two bits of the ctx pointer to store the handler ID.
149 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
150 * We can change this if it becomes a problem.
184d2944
MW		 151 *
152 * May be called with local interrupts disabled and the q_lock held,
153 * or with interrupts enabled and no locks held.
b60503ba 154 */
c2f5b650
MW		 155static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
156 nvme_completion_fn handler, unsigned timeout)
b60503ba 157{
e6d15f79 158 int depth = nvmeq->q_depth - 1;
e85248e5 159 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba
MW		 160 int cmdid;
161
b60503ba
MW		 162 do {
163 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
164 if (cmdid >= depth)
165 return -EBUSY;
166 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
167
c2f5b650
MW		 168 info[cmdid].fn = handler;
169 info[cmdid].ctx = ctx;
e85248e5 170 info[cmdid].timeout = jiffies + timeout;
c30341dc 171 info[cmdid].aborted = 0;
b60503ba
MW		 172 return cmdid;
173}
174
175static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 176 nvme_completion_fn handler, unsigned timeout)
b60503ba
MW		 177{
178 int cmdid;
179 wait_event_killable(nvmeq->sq_full,
e85248e5 180 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
b60503ba
MW		 181 return (cmdid < 0) ? -EINTR : cmdid;
182}
183
c2f5b650
MW		 184/* Special values must be less than 0x1000 */
185#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 186#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
187#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
188#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
00df5cb4 189#define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
c30341dc 190#define CMD_CTX_ABORT (0x31C + CMD_CTX_BASE)
be7b6275 191
5c1281a3 192static void special_completion(struct nvme_dev *dev, void *ctx,
c2f5b650
MW		 193 struct nvme_completion *cqe)
194{
195 if (ctx == CMD_CTX_CANCELLED)
196 return;
197 if (ctx == CMD_CTX_FLUSH)
198 return;
c30341dc
KB		 199 if (ctx == CMD_CTX_ABORT) {
200 ++dev->abort_limit;
201 return;
202 }
c2f5b650 203 if (ctx == CMD_CTX_COMPLETED) {
5c1281a3 204 dev_warn(&dev->pci_dev->dev,
c2f5b650
MW		 205 "completed id %d twice on queue %d\n",
206 cqe->command_id, le16_to_cpup(&cqe->sq_id));
207 return;
208 }
209 if (ctx == CMD_CTX_INVALID) {
5c1281a3 210 dev_warn(&dev->pci_dev->dev,
c2f5b650
MW		 211 "invalid id %d completed on queue %d\n",
212 cqe->command_id, le16_to_cpup(&cqe->sq_id));
213 return;
214 }
215
5c1281a3 216 dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 217}
218
4d115420
KB		 219static void async_completion(struct nvme_dev *dev, void *ctx,
220 struct nvme_completion *cqe)
221{
222 struct async_cmd_info *cmdinfo = ctx;
223 cmdinfo->result = le32_to_cpup(&cqe->result);
224 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
225 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
226}
227
184d2944
MW		 228/*
229 * Called with local interrupts disabled and the q_lock held. May not sleep.
230 */
c2f5b650
MW		 231static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
232 nvme_completion_fn *fn)
b60503ba 233{
c2f5b650 234 void *ctx;
e85248e5 235 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 236
c2f5b650
MW		 237 if (cmdid >= nvmeq->q_depth) {
238 *fn = special_completion;
48e3d398 239 return CMD_CTX_INVALID;
c2f5b650 240 }
859361a2
KB		 241 if (fn)
242 *fn = info[cmdid].fn;
c2f5b650
MW		 243 ctx = info[cmdid].ctx;
244 info[cmdid].fn = special_completion;
e85248e5 245 info[cmdid].ctx = CMD_CTX_COMPLETED;
b60503ba
MW		 246 clear_bit(cmdid, nvmeq->cmdid_data);
247 wake_up(&nvmeq->sq_full);
c2f5b650 248 return ctx;
b60503ba
MW		 249}
250
c2f5b650
MW		 251static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
252 nvme_completion_fn *fn)
3c0cf138 253{
c2f5b650 254 void *ctx;
e85248e5 255 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
c2f5b650
MW		 256 if (fn)
257 *fn = info[cmdid].fn;
258 ctx = info[cmdid].ctx;
259 info[cmdid].fn = special_completion;
e85248e5 260 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 261 return ctx;
3c0cf138
MW		 262}
263
5d0f6131 264struct nvme_queue *get_nvmeq(struct nvme_dev *dev)
b60503ba 265{
040a93b5 266 return dev->queues[get_cpu() + 1];
b60503ba
MW		 267}
268
5d0f6131 269void put_nvmeq(struct nvme_queue *nvmeq)
b60503ba 270{
1b23484b 271 put_cpu();
b60503ba
MW		 272}
273
274/**
714a7a22 275 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 276 * @nvmeq: The queue to use
277 * @cmd: The command to send
278 *
279 * Safe to use from interrupt context
280 */
281static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
282{
283 unsigned long flags;
284 u16 tail;
b60503ba
MW		 285 spin_lock_irqsave(&nvmeq->q_lock, flags);
286 tail = nvmeq->sq_tail;
287 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 288 if (++tail == nvmeq->q_depth)
289 tail = 0;
7547881d 290 writel(tail, nvmeq->q_db);
b60503ba
MW		 291 nvmeq->sq_tail = tail;
292 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
293
294 return 0;
295}
296
eca18b23 297static __le64 **iod_list(struct nvme_iod *iod)
e025344c 298{
eca18b23 299 return ((void *)iod) + iod->offset;
e025344c
SMM		 300}
301
eca18b23
MW		 302/*
303 * Will slightly overestimate the number of pages needed. This is OK
304 * as it only leads to a small amount of wasted memory for the lifetime of
305 * the I/O.
306 */
307static int nvme_npages(unsigned size)
308{
309 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
310 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
311}
b60503ba 312
eca18b23
MW		 313static struct nvme_iod *
314nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
b60503ba 315{
eca18b23
MW		 316 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
317 sizeof(__le64 *) * nvme_npages(nbytes) +
318 sizeof(struct scatterlist) * nseg, gfp);
319
320 if (iod) {
321 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
322 iod->npages = -1;
323 iod->length = nbytes;
2b196034 324 iod->nents = 0;
6198221f 325 iod->start_time = jiffies;
eca18b23
MW		 326 }
327
328 return iod;
b60503ba
MW		 329}
330
5d0f6131 331void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 332{
eca18b23
MW		 333 const int last_prp = PAGE_SIZE / 8 - 1;
334 int i;
335 __le64 **list = iod_list(iod);
336 dma_addr_t prp_dma = iod->first_dma;
337
338 if (iod->npages == 0)
339 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
340 for (i = 0; i < iod->npages; i++) {
341 __le64 *prp_list = list[i];
342 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
343 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
344 prp_dma = next_prp_dma;
345 }
346 kfree(iod);
b60503ba
MW		 347}
348
6198221f
KB		 349static void nvme_start_io_acct(struct bio *bio)
350{
351 struct gendisk *disk = bio->bi_bdev->bd_disk;
352 const int rw = bio_data_dir(bio);
353 int cpu = part_stat_lock();
354 part_round_stats(cpu, &disk->part0);
355 part_stat_inc(cpu, &disk->part0, ios[rw]);
356 part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio));
357 part_inc_in_flight(&disk->part0, rw);
358 part_stat_unlock();
359}
360
361static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
362{
363 struct gendisk *disk = bio->bi_bdev->bd_disk;
364 const int rw = bio_data_dir(bio);
365 unsigned long duration = jiffies - start_time;
366 int cpu = part_stat_lock();
367 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
368 part_round_stats(cpu, &disk->part0);
369 part_dec_in_flight(&disk->part0, rw);
370 part_stat_unlock();
371}
372
5c1281a3 373static void bio_completion(struct nvme_dev *dev, void *ctx,
b60503ba
MW		 374 struct nvme_completion *cqe)
375{
eca18b23
MW		 376 struct nvme_iod *iod = ctx;
377 struct bio *bio = iod->private;
b60503ba
MW		 378 u16 status = le16_to_cpup(&cqe->status) >> 1;
379
9e59d091 380 if (iod->nents) {
2b196034 381 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
b60503ba 382 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9e59d091
KB		 383 nvme_end_io_acct(bio, iod->start_time);
384 }
eca18b23 385 nvme_free_iod(dev, iod);
427e9708 386 if (status)
1ad2f893 387 bio_endio(bio, -EIO);
427e9708 388 else
1ad2f893 389 bio_endio(bio, 0);
b60503ba
MW		 390}
391
184d2944 392/* length is in bytes. gfp flags indicates whether we may sleep. */
5d0f6131
VV		 393int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd,
394 struct nvme_iod *iod, int total_len, gfp_t gfp)
ff22b54f 395{
99802a7a 396 struct dma_pool *pool;
eca18b23
MW		 397 int length = total_len;
398 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 399 int dma_len = sg_dma_len(sg);
400 u64 dma_addr = sg_dma_address(sg);
401 int offset = offset_in_page(dma_addr);
e025344c 402 __le64 *prp_list;
eca18b23 403 __le64 **list = iod_list(iod);
e025344c 404 dma_addr_t prp_dma;
eca18b23 405 int nprps, i;
ff22b54f
MW		 406
407 cmd->prp1 = cpu_to_le64(dma_addr);
408 length -= (PAGE_SIZE - offset);
409 if (length <= 0)
eca18b23 410 return total_len;
ff22b54f
MW		 411
412 dma_len -= (PAGE_SIZE - offset);
413 if (dma_len) {
414 dma_addr += (PAGE_SIZE - offset);
415 } else {
416 sg = sg_next(sg);
417 dma_addr = sg_dma_address(sg);
418 dma_len = sg_dma_len(sg);
419 }
420
421 if (length <= PAGE_SIZE) {
422 cmd->prp2 = cpu_to_le64(dma_addr);
eca18b23 423 return total_len;
e025344c
SMM		 424 }
425
426 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
99802a7a
MW		 427 if (nprps <= (256 / 8)) {
428 pool = dev->prp_small_pool;
eca18b23 429 iod->npages = 0;
99802a7a
MW		 430 } else {
431 pool = dev->prp_page_pool;
eca18b23 432 iod->npages = 1;
99802a7a
MW		 433 }
434
b77954cb
MW		 435 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
436 if (!prp_list) {
437 cmd->prp2 = cpu_to_le64(dma_addr);
eca18b23
MW		 438 iod->npages = -1;
439 return (total_len - length) + PAGE_SIZE;
b77954cb 440 }
eca18b23
MW		 441 list[0] = prp_list;
442 iod->first_dma = prp_dma;
e025344c
SMM		 443 cmd->prp2 = cpu_to_le64(prp_dma);
444 i = 0;
445 for (;;) {
7523d834 446 if (i == PAGE_SIZE / 8) {
e025344c 447 __le64 *old_prp_list = prp_list;
b77954cb 448 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 449 if (!prp_list)
450 return total_len - length;
451 list[iod->npages++] = prp_list;
7523d834
MW		 452 prp_list[0] = old_prp_list[i - 1];
453 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
454 i = 1;
e025344c
SMM		 455 }
456 prp_list[i++] = cpu_to_le64(dma_addr);
457 dma_len -= PAGE_SIZE;
458 dma_addr += PAGE_SIZE;
459 length -= PAGE_SIZE;
460 if (length <= 0)
461 break;
462 if (dma_len > 0)
463 continue;
464 BUG_ON(dma_len < 0);
465 sg = sg_next(sg);
466 dma_addr = sg_dma_address(sg);
467 dma_len = sg_dma_len(sg);
ff22b54f
MW		 468 }
469
eca18b23 470 return total_len;
ff22b54f
MW		 471}
472
427e9708
KB		 473struct nvme_bio_pair {
474 struct bio b1, b2, *parent;
475 struct bio_vec *bv1, *bv2;
476 int err;
477 atomic_t cnt;
478};
479
480static void nvme_bio_pair_endio(struct bio *bio, int err)
481{
482 struct nvme_bio_pair *bp = bio->bi_private;
483
484 if (err)
485 bp->err = err;
486
487 if (atomic_dec_and_test(&bp->cnt)) {
488 bio_endio(bp->parent, bp->err);
1b56749e
KB		 489 kfree(bp->bv1);
490 kfree(bp->bv2);
427e9708
KB		 491 kfree(bp);
492 }
493}
494
495static struct nvme_bio_pair *nvme_bio_split(struct bio *bio, int idx,
496 int len, int offset)
497{
498 struct nvme_bio_pair *bp;
499
500 BUG_ON(len > bio->bi_size);
501 BUG_ON(idx > bio->bi_vcnt);
502
503 bp = kmalloc(sizeof(*bp), GFP_ATOMIC);
504 if (!bp)
505 return NULL;
506 bp->err = 0;
507
508 bp->b1 = *bio;
509 bp->b2 = *bio;
510
511 bp->b1.bi_size = len;
512 bp->b2.bi_size -= len;
513 bp->b1.bi_vcnt = idx;
514 bp->b2.bi_idx = idx;
515 bp->b2.bi_sector += len >> 9;
516
517 if (offset) {
518 bp->bv1 = kmalloc(bio->bi_max_vecs * sizeof(struct bio_vec),
519 GFP_ATOMIC);
520 if (!bp->bv1)
521 goto split_fail_1;
522
523 bp->bv2 = kmalloc(bio->bi_max_vecs * sizeof(struct bio_vec),
524 GFP_ATOMIC);
525 if (!bp->bv2)
526 goto split_fail_2;
527
528 memcpy(bp->bv1, bio->bi_io_vec,
529 bio->bi_max_vecs * sizeof(struct bio_vec));
530 memcpy(bp->bv2, bio->bi_io_vec,
531 bio->bi_max_vecs * sizeof(struct bio_vec));
532
533 bp->b1.bi_io_vec = bp->bv1;
534 bp->b2.bi_io_vec = bp->bv2;
535 bp->b2.bi_io_vec[idx].bv_offset += offset;
536 bp->b2.bi_io_vec[idx].bv_len -= offset;
537 bp->b1.bi_io_vec[idx].bv_len = offset;
538 bp->b1.bi_vcnt++;
539 } else
540 bp->bv1 = bp->bv2 = NULL;
541
542 bp->b1.bi_private = bp;
543 bp->b2.bi_private = bp;
544
545 bp->b1.bi_end_io = nvme_bio_pair_endio;
546 bp->b2.bi_end_io = nvme_bio_pair_endio;
547
548 bp->parent = bio;
549 atomic_set(&bp->cnt, 2);
550
551 return bp;
552
553 split_fail_2:
554 kfree(bp->bv1);
555 split_fail_1:
556 kfree(bp);
557 return NULL;
558}
559
560static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
561 int idx, int len, int offset)
562{
563 struct nvme_bio_pair *bp = nvme_bio_split(bio, idx, len, offset);
564 if (!bp)
565 return -ENOMEM;
566
567 if (bio_list_empty(&nvmeq->sq_cong))
568 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
569 bio_list_add(&nvmeq->sq_cong, &bp->b1);
570 bio_list_add(&nvmeq->sq_cong, &bp->b2);
571
572 return 0;
573}
574
1ad2f893
MW		 575/* NVMe scatterlists require no holes in the virtual address */
576#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
577 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
578
427e9708 579static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
b60503ba
MW		 580 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
581{
76830840
MW		 582 struct bio_vec *bvec, *bvprv = NULL;
583 struct scatterlist *sg = NULL;
159b67d7
KB		 584 int i, length = 0, nsegs = 0, split_len = bio->bi_size;
585
586 if (nvmeq->dev->stripe_size)
587 split_len = nvmeq->dev->stripe_size -
588 ((bio->bi_sector << 9) & (nvmeq->dev->stripe_size - 1));
b60503ba 589
eca18b23 590 sg_init_table(iod->sg, psegs);
b60503ba 591 bio_for_each_segment(bvec, bio, i) {
76830840
MW		 592 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
593 sg->length += bvec->bv_len;
594 } else {
1ad2f893 595 if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
427e9708
KB		 596 return nvme_split_and_submit(bio, nvmeq, i,
597 length, 0);
598
eca18b23 599 sg = sg ? sg + 1 : iod->sg;
76830840
MW		 600 sg_set_page(sg, bvec->bv_page, bvec->bv_len,
601 bvec->bv_offset);
602 nsegs++;
603 }
159b67d7
KB		 604
605 if (split_len - length < bvec->bv_len)
606 return nvme_split_and_submit(bio, nvmeq, i, split_len,
607 split_len - length);
1ad2f893 608 length += bvec->bv_len;
76830840 609 bvprv = bvec;
b60503ba 610 }
eca18b23 611 iod->nents = nsegs;
76830840 612 sg_mark_end(sg);
427e9708 613 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
1ad2f893 614 return -ENOMEM;
427e9708 615
159b67d7 616 BUG_ON(length != bio->bi_size);
1ad2f893 617 return length;
b60503ba
MW		 618}
619
0e5e4f0e
KB		 620/*
621 * We reuse the small pool to allocate the 16-byte range here as it is not
622 * worth having a special pool for these or additional cases to handle freeing
623 * the iod.
624 */
625static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
626 struct bio *bio, struct nvme_iod *iod, int cmdid)
627{
628 struct nvme_dsm_range *range;
629 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
630
631 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
632 &iod->first_dma);
633 if (!range)
634 return -ENOMEM;
635
636 iod_list(iod)[0] = (__le64 *)range;
637 iod->npages = 0;
638
639 range->cattr = cpu_to_le32(0);
640 range->nlb = cpu_to_le32(bio->bi_size >> ns->lba_shift);
063cc6d5 641 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_sector));
0e5e4f0e
KB		 642
643 memset(cmnd, 0, sizeof(*cmnd));
644 cmnd->dsm.opcode = nvme_cmd_dsm;
645 cmnd->dsm.command_id = cmdid;
646 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
647 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
648 cmnd->dsm.nr = 0;
649 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
650
651 if (++nvmeq->sq_tail == nvmeq->q_depth)
652 nvmeq->sq_tail = 0;
653 writel(nvmeq->sq_tail, nvmeq->q_db);
654
655 return 0;
656}
657
00df5cb4
MW		 658static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
659 int cmdid)
660{
661 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
662
663 memset(cmnd, 0, sizeof(*cmnd));
664 cmnd->common.opcode = nvme_cmd_flush;
665 cmnd->common.command_id = cmdid;
666 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
667
668 if (++nvmeq->sq_tail == nvmeq->q_depth)
669 nvmeq->sq_tail = 0;
670 writel(nvmeq->sq_tail, nvmeq->q_db);
671
672 return 0;
673}
674
5d0f6131 675int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
00df5cb4
MW		 676{
677 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
ff976d72 678 special_completion, NVME_IO_TIMEOUT);
00df5cb4
MW		 679 if (unlikely(cmdid < 0))
680 return cmdid;
681
682 return nvme_submit_flush(nvmeq, ns, cmdid);
683}
684
184d2944
MW		 685/*
686 * Called with local interrupts disabled and the q_lock held. May not sleep.
687 */
b60503ba
MW		 688static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
689 struct bio *bio)
690{
ff22b54f 691 struct nvme_command *cmnd;
eca18b23 692 struct nvme_iod *iod;
b60503ba 693 enum dma_data_direction dma_dir;
1287dabd 694 int cmdid, length, result;
b60503ba
MW		 695 u16 control;
696 u32 dsmgmt;
b60503ba
MW		 697 int psegs = bio_phys_segments(ns->queue, bio);
698
00df5cb4
MW		 699 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
700 result = nvme_submit_flush_data(nvmeq, ns);
701 if (result)
702 return result;
703 }
704
1287dabd 705 result = -ENOMEM;
eca18b23
MW		 706 iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC);
707 if (!iod)
eeee3226 708 goto nomem;
eca18b23 709 iod->private = bio;
b60503ba 710
eeee3226 711 result = -EBUSY;
ff976d72 712 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 713 if (unlikely(cmdid < 0))
eca18b23 714 goto free_iod;
b60503ba 715
0e5e4f0e
KB		 716 if (bio->bi_rw & REQ_DISCARD) {
717 result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
718 if (result)
719 goto free_cmdid;
720 return result;
721 }
00df5cb4
MW		 722 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
723 return nvme_submit_flush(nvmeq, ns, cmdid);
724
b60503ba
MW		 725 control = 0;
726 if (bio->bi_rw & REQ_FUA)
727 control |= NVME_RW_FUA;
728 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
729 control |= NVME_RW_LR;
730
731 dsmgmt = 0;
732 if (bio->bi_rw & REQ_RAHEAD)
733 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
734
ff22b54f 735 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b60503ba 736
b8deb62c 737 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 738 if (bio_data_dir(bio)) {
ff22b54f 739 cmnd->rw.opcode = nvme_cmd_write;
b60503ba
MW		 740 dma_dir = DMA_TO_DEVICE;
741 } else {
ff22b54f 742 cmnd->rw.opcode = nvme_cmd_read;
b60503ba
MW		 743 dma_dir = DMA_FROM_DEVICE;
744 }
745
427e9708
KB		 746 result = nvme_map_bio(nvmeq, iod, bio, dma_dir, psegs);
747 if (result <= 0)
859361a2 748 goto free_cmdid;
1ad2f893 749 length = result;
b60503ba 750
ff22b54f
MW		 751 cmnd->rw.command_id = cmdid;
752 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
eca18b23
MW		 753 length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
754 GFP_ATOMIC);
063cc6d5 755 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_sector));
1ad2f893 756 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
ff22b54f
MW		 757 cmnd->rw.control = cpu_to_le16(control);
758 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 759
6198221f 760 nvme_start_io_acct(bio);
b60503ba
MW		 761 if (++nvmeq->sq_tail == nvmeq->q_depth)
762 nvmeq->sq_tail = 0;
7547881d 763 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 764
1974b1ae
MW		 765 return 0;
766
859361a2
KB		 767 free_cmdid:
768 free_cmdid(nvmeq, cmdid, NULL);
eca18b23
MW		 769 free_iod:
770 nvme_free_iod(nvmeq->dev, iod);
eeee3226
MW		 771 nomem:
772 return result;
b60503ba
MW		 773}
774
e9539f47 775static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 776{
82123460 777 u16 head, phase;
b60503ba 778
b60503ba 779 head = nvmeq->cq_head;
82123460 780 phase = nvmeq->cq_phase;
b60503ba
MW		 781
782 for (;;) {
c2f5b650
MW		 783 void *ctx;
784 nvme_completion_fn fn;
b60503ba 785 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 786 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 787 break;
788 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
789 if (++head == nvmeq->q_depth) {
790 head = 0;
82123460 791 phase = !phase;
b60503ba
MW		 792 }
793
c2f5b650 794 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
5c1281a3 795 fn(nvmeq->dev, ctx, &cqe);
b60503ba
MW		 796 }
797
798 /* If the controller ignores the cq head doorbell and continuously
799 * writes to the queue, it is theoretically possible to wrap around
800 * the queue twice and mistakenly return IRQ_NONE. Linux only
801 * requires that 0.1% of your interrupts are handled, so this isn't
802 * a big problem.
803 */
82123460 804 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 805 return 0;
b60503ba 806
b80d5ccc 807 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 808 nvmeq->cq_head = head;
82123460 809 nvmeq->cq_phase = phase;
b60503ba 810
e9539f47
MW		 811 nvmeq->cqe_seen = 1;
812 return 1;
b60503ba
MW		 813}
814
7d822457
MW		 815static void nvme_make_request(struct request_queue *q, struct bio *bio)
816{
817 struct nvme_ns *ns = q->queuedata;
818 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
819 int result = -EBUSY;
820
cd638946
KB		 821 if (!nvmeq) {
822 put_nvmeq(NULL);
823 bio_endio(bio, -EIO);
824 return;
825 }
826
7d822457 827 spin_lock_irq(&nvmeq->q_lock);
22404274 828 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
7d822457
MW		 829 result = nvme_submit_bio_queue(nvmeq, ns, bio);
830 if (unlikely(result)) {
831 if (bio_list_empty(&nvmeq->sq_cong))
832 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
833 bio_list_add(&nvmeq->sq_cong, bio);
834 }
835
836 nvme_process_cq(nvmeq);
837 spin_unlock_irq(&nvmeq->q_lock);
838 put_nvmeq(nvmeq);
839}
840
b60503ba 841static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 842{
843 irqreturn_t result;
844 struct nvme_queue *nvmeq = data;
845 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 846 nvme_process_cq(nvmeq);
847 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
848 nvmeq->cqe_seen = 0;
58ffacb5
MW		 849 spin_unlock(&nvmeq->q_lock);
850 return result;
851}
852
853static irqreturn_t nvme_irq_check(int irq, void *data)
854{
855 struct nvme_queue *nvmeq = data;
856 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
857 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
858 return IRQ_NONE;
859 return IRQ_WAKE_THREAD;
860}
861
3c0cf138
MW		 862static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
863{
864 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 865 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW		 866 spin_unlock_irq(&nvmeq->q_lock);
867}
868
c2f5b650
MW		 869struct sync_cmd_info {
870 struct task_struct *task;
871 u32 result;
872 int status;
873};
874
5c1281a3 875static void sync_completion(struct nvme_dev *dev, void *ctx,
c2f5b650
MW		 876 struct nvme_completion *cqe)
877{
878 struct sync_cmd_info *cmdinfo = ctx;
879 cmdinfo->result = le32_to_cpup(&cqe->result);
880 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
881 wake_up_process(cmdinfo->task);
882}
883
b60503ba
MW		 884/*
885 * Returns 0 on success. If the result is negative, it's a Linux error code;
886 * if the result is positive, it's an NVM Express status code
887 */
5d0f6131
VV		 888int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
889 u32 *result, unsigned timeout)
b60503ba
MW		 890{
891 int cmdid;
892 struct sync_cmd_info cmdinfo;
893
894 cmdinfo.task = current;
895 cmdinfo.status = -EINTR;
896
c2f5b650 897 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion,
e85248e5 898 timeout);
b60503ba
MW		 899 if (cmdid < 0)
900 return cmdid;
901 cmd->common.command_id = cmdid;
902
3c0cf138
MW		 903 set_current_state(TASK_KILLABLE);
904 nvme_submit_cmd(nvmeq, cmd);
78f8d257 905 schedule_timeout(timeout);
b60503ba 906
3c0cf138
MW		 907 if (cmdinfo.status == -EINTR) {
908 nvme_abort_command(nvmeq, cmdid);
909 return -EINTR;
910 }
911
b60503ba
MW		 912 if (result)
913 *result = cmdinfo.result;
914
915 return cmdinfo.status;
916}
917
4d115420
KB		 918static int nvme_submit_async_cmd(struct nvme_queue *nvmeq,
919 struct nvme_command *cmd,
920 struct async_cmd_info *cmdinfo, unsigned timeout)
921{
922 int cmdid;
923
924 cmdid = alloc_cmdid_killable(nvmeq, cmdinfo, async_completion, timeout);
925 if (cmdid < 0)
926 return cmdid;
927 cmdinfo->status = -EINTR;
928 cmd->common.command_id = cmdid;
929 nvme_submit_cmd(nvmeq, cmd);
930 return 0;
931}
932
5d0f6131 933int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
b60503ba
MW		 934 u32 *result)
935{
e85248e5 936 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 937}
938
4d115420
KB		 939static int nvme_submit_admin_cmd_async(struct nvme_dev *dev,
940 struct nvme_command *cmd, struct async_cmd_info *cmdinfo)
941{
942 return nvme_submit_async_cmd(dev->queues[0], cmd, cmdinfo,
943 ADMIN_TIMEOUT);
944}
945
b60503ba
MW		 946static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
947{
948 int status;
949 struct nvme_command c;
950
951 memset(&c, 0, sizeof(c));
952 c.delete_queue.opcode = opcode;
953 c.delete_queue.qid = cpu_to_le16(id);
954
955 status = nvme_submit_admin_cmd(dev, &c, NULL);
956 if (status)
957 return -EIO;
958 return 0;
959}
960
961static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
962 struct nvme_queue *nvmeq)
963{
964 int status;
965 struct nvme_command c;
966 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
967
968 memset(&c, 0, sizeof(c));
969 c.create_cq.opcode = nvme_admin_create_cq;
970 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
971 c.create_cq.cqid = cpu_to_le16(qid);
972 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
973 c.create_cq.cq_flags = cpu_to_le16(flags);
974 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
975
976 status = nvme_submit_admin_cmd(dev, &c, NULL);
977 if (status)
978 return -EIO;
979 return 0;
980}
981
982static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
983 struct nvme_queue *nvmeq)
984{
985 int status;
986 struct nvme_command c;
987 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
988
989 memset(&c, 0, sizeof(c));
990 c.create_sq.opcode = nvme_admin_create_sq;
991 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
992 c.create_sq.sqid = cpu_to_le16(qid);
993 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
994 c.create_sq.sq_flags = cpu_to_le16(flags);
995 c.create_sq.cqid = cpu_to_le16(qid);
996
997 status = nvme_submit_admin_cmd(dev, &c, NULL);
998 if (status)
999 return -EIO;
1000 return 0;
1001}
1002
1003static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1004{
1005 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1006}
1007
1008static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1009{
1010 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1011}
1012
5d0f6131 1013int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 1014 dma_addr_t dma_addr)
1015{
1016 struct nvme_command c;
1017
1018 memset(&c, 0, sizeof(c));
1019 c.identify.opcode = nvme_admin_identify;
1020 c.identify.nsid = cpu_to_le32(nsid);
1021 c.identify.prp1 = cpu_to_le64(dma_addr);
1022 c.identify.cns = cpu_to_le32(cns);
1023
1024 return nvme_submit_admin_cmd(dev, &c, NULL);
1025}
1026
5d0f6131 1027int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1028 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1029{
1030 struct nvme_command c;
1031
1032 memset(&c, 0, sizeof(c));
1033 c.features.opcode = nvme_admin_get_features;
a42cecce 1034 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1035 c.features.prp1 = cpu_to_le64(dma_addr);
1036 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1037
08df1e05 1038 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 1039}
1040
5d0f6131
VV		 1041int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1042 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1043{
1044 struct nvme_command c;
1045
1046 memset(&c, 0, sizeof(c));
1047 c.features.opcode = nvme_admin_set_features;
1048 c.features.prp1 = cpu_to_le64(dma_addr);
1049 c.features.fid = cpu_to_le32(fid);
1050 c.features.dword11 = cpu_to_le32(dword11);
1051
bc5fc7e4
MW		 1052 return nvme_submit_admin_cmd(dev, &c, result);
1053}
1054
c30341dc
KB		 1055/**
1056 * nvme_abort_cmd - Attempt aborting a command
1057 * @cmdid: Command id of a timed out IO
1058 * @queue: The queue with timed out IO
1059 *
1060 * Schedule controller reset if the command was already aborted once before and
1061 * still hasn't been returned to the driver, or if this is the admin queue.
1062 */
1063static void nvme_abort_cmd(int cmdid, struct nvme_queue *nvmeq)
1064{
1065 int a_cmdid;
1066 struct nvme_command cmd;
1067 struct nvme_dev *dev = nvmeq->dev;
1068 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1069
1070 if (!nvmeq->qid || info[cmdid].aborted) {
1071 if (work_busy(&dev->reset_work))
1072 return;
1073 list_del_init(&dev->node);
1074 dev_warn(&dev->pci_dev->dev,
1075 "I/O %d QID %d timeout, reset controller\n", cmdid,
1076 nvmeq->qid);
1077 INIT_WORK(&dev->reset_work, nvme_reset_failed_dev);
1078 queue_work(nvme_workq, &dev->reset_work);
1079 return;
1080 }
1081
1082 if (!dev->abort_limit)
1083 return;
1084
1085 a_cmdid = alloc_cmdid(dev->queues[0], CMD_CTX_ABORT, special_completion,
1086 ADMIN_TIMEOUT);
1087 if (a_cmdid < 0)
1088 return;
1089
1090 memset(&cmd, 0, sizeof(cmd));
1091 cmd.abort.opcode = nvme_admin_abort_cmd;
1092 cmd.abort.cid = cmdid;
1093 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1094 cmd.abort.command_id = a_cmdid;
1095
1096 --dev->abort_limit;
1097 info[cmdid].aborted = 1;
1098 info[cmdid].timeout = jiffies + ADMIN_TIMEOUT;
1099
1100 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", cmdid,
1101 nvmeq->qid);
1102 nvme_submit_cmd(dev->queues[0], &cmd);
1103}
1104
a09115b2
MW		 1105/**
1106 * nvme_cancel_ios - Cancel outstanding I/Os
1107 * @queue: The queue to cancel I/Os on
1108 * @timeout: True to only cancel I/Os which have timed out
1109 */
1110static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1111{
1112 int depth = nvmeq->q_depth - 1;
1113 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1114 unsigned long now = jiffies;
1115 int cmdid;
1116
1117 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1118 void *ctx;
1119 nvme_completion_fn fn;
1120 static struct nvme_completion cqe = {
af2d9ca7 1121 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
a09115b2
MW		 1122 };
1123
1124 if (timeout && !time_after(now, info[cmdid].timeout))
1125 continue;
053ab702
KB		 1126 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1127 continue;
c30341dc
KB		 1128 if (timeout && nvmeq->dev->initialized) {
1129 nvme_abort_cmd(cmdid, nvmeq);
1130 continue;
1131 }
1132 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", cmdid,
1133 nvmeq->qid);
a09115b2
MW		 1134 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
1135 fn(nvmeq->dev, ctx, &cqe);
1136 }
1137}
1138
22404274 1139static void nvme_free_queue(struct nvme_queue *nvmeq)
9e866774 1140{
22404274
KB		 1141 spin_lock_irq(&nvmeq->q_lock);
1142 while (bio_list_peek(&nvmeq->sq_cong)) {
1143 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1144 bio_endio(bio, -EIO);
1145 }
1146 spin_unlock_irq(&nvmeq->q_lock);
1147
9e866774
MW		 1148 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1149 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1150 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1151 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1152 kfree(nvmeq);
1153}
1154
a1a5ef99 1155static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1156{
1157 int i;
1158
a1a5ef99 1159 for (i = dev->queue_count - 1; i >= lowest; i--) {
22404274
KB		 1160 nvme_free_queue(dev->queues[i]);
1161 dev->queue_count--;
1162 dev->queues[i] = NULL;
1163 }
1164}
1165
4d115420
KB		 1166/**
1167 * nvme_suspend_queue - put queue into suspended state
1168 * @nvmeq - queue to suspend
1169 *
1170 * Returns 1 if already suspended, 0 otherwise.
1171 */
1172static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1173{
4d115420 1174 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1175
a09115b2 1176 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1177 if (nvmeq->q_suspended) {
1178 spin_unlock_irq(&nvmeq->q_lock);
4d115420 1179 return 1;
3295874b 1180 }
22404274 1181 nvmeq->q_suspended = 1;
a09115b2
MW		 1182 spin_unlock_irq(&nvmeq->q_lock);
1183
aba2080f
MW		 1184 irq_set_affinity_hint(vector, NULL);
1185 free_irq(vector, nvmeq);
b60503ba 1186
4d115420
KB		 1187 return 0;
1188}
1189
1190static void nvme_clear_queue(struct nvme_queue *nvmeq)
1191{
1192 spin_lock_irq(&nvmeq->q_lock);
1193 nvme_process_cq(nvmeq);
1194 nvme_cancel_ios(nvmeq, false);
1195 spin_unlock_irq(&nvmeq->q_lock);
1196}
1197
1198static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1199{
1200 struct nvme_queue *nvmeq = dev->queues[qid];
1201
1202 if (!nvmeq)
1203 return;
1204 if (nvme_suspend_queue(nvmeq))
1205 return;
1206
0e53d180
KB		 1207 /* Don't tell the adapter to delete the admin queue.
1208 * Don't tell a removed adapter to delete IO queues. */
1209 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1210 adapter_delete_sq(dev, qid);
1211 adapter_delete_cq(dev, qid);
1212 }
4d115420 1213 nvme_clear_queue(nvmeq);
b60503ba
MW		 1214}
1215
1216static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1217 int depth, int vector)
1218{
1219 struct device *dmadev = &dev->pci_dev->dev;
22404274 1220 unsigned extra = nvme_queue_extra(depth);
b60503ba
MW		 1221 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1222 if (!nvmeq)
1223 return NULL;
1224
1225 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1226 &nvmeq->cq_dma_addr, GFP_KERNEL);
1227 if (!nvmeq->cqes)
1228 goto free_nvmeq;
1229 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1230
1231 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1232 &nvmeq->sq_dma_addr, GFP_KERNEL);
1233 if (!nvmeq->sq_cmds)
1234 goto free_cqdma;
1235
1236 nvmeq->q_dmadev = dmadev;
091b6092 1237 nvmeq->dev = dev;
b60503ba
MW		 1238 spin_lock_init(&nvmeq->q_lock);
1239 nvmeq->cq_head = 0;
82123460 1240 nvmeq->cq_phase = 1;
b60503ba 1241 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1242 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1243 bio_list_init(&nvmeq->sq_cong);
b80d5ccc 1244 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW		 1245 nvmeq->q_depth = depth;
1246 nvmeq->cq_vector = vector;
c30341dc 1247 nvmeq->qid = qid;
22404274
KB		 1248 nvmeq->q_suspended = 1;
1249 dev->queue_count++;
b60503ba
MW		 1250
1251 return nvmeq;
1252
1253 free_cqdma:
68b8eca5 1254 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1255 nvmeq->cq_dma_addr);
1256 free_nvmeq:
1257 kfree(nvmeq);
1258 return NULL;
1259}
1260
3001082c
MW		 1261static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1262 const char *name)
1263{
58ffacb5
MW		 1264 if (use_threaded_interrupts)
1265 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1266 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1267 name, nvmeq);
3001082c 1268 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1269 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1270}
1271
22404274 1272static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1273{
22404274
KB		 1274 struct nvme_dev *dev = nvmeq->dev;
1275 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
b60503ba 1276
22404274
KB		 1277 nvmeq->sq_tail = 0;
1278 nvmeq->cq_head = 0;
1279 nvmeq->cq_phase = 1;
b80d5ccc 1280 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274
KB		 1281 memset(nvmeq->cmdid_data, 0, extra);
1282 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1283 nvme_cancel_ios(nvmeq, false);
1284 nvmeq->q_suspended = 0;
1285}
1286
1287static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1288{
1289 struct nvme_dev *dev = nvmeq->dev;
1290 int result;
3f85d50b 1291
b60503ba
MW		 1292 result = adapter_alloc_cq(dev, qid, nvmeq);
1293 if (result < 0)
22404274 1294 return result;
b60503ba
MW		 1295
1296 result = adapter_alloc_sq(dev, qid, nvmeq);
1297 if (result < 0)
1298 goto release_cq;
1299
3001082c 1300 result = queue_request_irq(dev, nvmeq, "nvme");
b60503ba
MW		 1301 if (result < 0)
1302 goto release_sq;
1303
0a8d44cb 1304 spin_lock_irq(&nvmeq->q_lock);
22404274 1305 nvme_init_queue(nvmeq, qid);
0a8d44cb 1306 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1307
1308 return result;
b60503ba
MW		 1309
1310 release_sq:
1311 adapter_delete_sq(dev, qid);
1312 release_cq:
1313 adapter_delete_cq(dev, qid);
22404274 1314 return result;
b60503ba
MW		 1315}
1316
ba47e386
MW		 1317static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1318{
1319 unsigned long timeout;
1320 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1321
1322 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1323
1324 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1325 msleep(100);
1326 if (fatal_signal_pending(current))
1327 return -EINTR;
1328 if (time_after(jiffies, timeout)) {
1329 dev_err(&dev->pci_dev->dev,
1330 "Device not ready; aborting initialisation\n");
1331 return -ENODEV;
1332 }
1333 }
1334
1335 return 0;
1336}
1337
1338/*
1339 * If the device has been passed off to us in an enabled state, just clear
1340 * the enabled bit. The spec says we should set the 'shutdown notification
1341 * bits', but doing so may cause the device to complete commands to the
1342 * admin queue ... and we don't know what memory that might be pointing at!
1343 */
1344static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1345{
44af146a
MW		 1346 u32 cc = readl(&dev->bar->cc);
1347
1348 if (cc & NVME_CC_ENABLE)
1349 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
ba47e386
MW		 1350 return nvme_wait_ready(dev, cap, false);
1351}
1352
1353static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1354{
1355 return nvme_wait_ready(dev, cap, true);
1356}
1357
1894d8f1
KB		 1358static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1359{
1360 unsigned long timeout;
1361 u32 cc;
1362
1363 cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
1364 writel(cc, &dev->bar->cc);
1365
1366 timeout = 2 * HZ + jiffies;
1367 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1368 NVME_CSTS_SHST_CMPLT) {
1369 msleep(100);
1370 if (fatal_signal_pending(current))
1371 return -EINTR;
1372 if (time_after(jiffies, timeout)) {
1373 dev_err(&dev->pci_dev->dev,
1374 "Device shutdown incomplete; abort shutdown\n");
1375 return -ENODEV;
1376 }
1377 }
1378
1379 return 0;
1380}
1381
8d85fce7 1382static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1383{
ba47e386 1384 int result;
b60503ba 1385 u32 aqa;
ba47e386 1386 u64 cap = readq(&dev->bar->cap);
b60503ba
MW		 1387 struct nvme_queue *nvmeq;
1388
ba47e386
MW		 1389 result = nvme_disable_ctrl(dev, cap);
1390 if (result < 0)
1391 return result;
b60503ba 1392
cd638946
KB		 1393 nvmeq = dev->queues[0];
1394 if (!nvmeq) {
1395 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1396 if (!nvmeq)
1397 return -ENOMEM;
1398 dev->queues[0] = nvmeq;
1399 }
b60503ba
MW		 1400
1401 aqa = nvmeq->q_depth - 1;
1402 aqa |= aqa << 16;
1403
1404 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1405 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1406 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1407 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1408
1409 writel(aqa, &dev->bar->aqa);
1410 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1411 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1412 writel(dev->ctrl_config, &dev->bar->cc);
1413
ba47e386 1414 result = nvme_enable_ctrl(dev, cap);
025c557a 1415 if (result)
cd638946 1416 return result;
9e866774 1417
3001082c 1418 result = queue_request_irq(dev, nvmeq, "nvme admin");
025c557a 1419 if (result)
cd638946 1420 return result;
025c557a 1421
0a8d44cb 1422 spin_lock_irq(&nvmeq->q_lock);
22404274 1423 nvme_init_queue(nvmeq, 0);
0a8d44cb 1424 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1425 return result;
1426}
1427
5d0f6131 1428struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1429 unsigned long addr, unsigned length)
b60503ba 1430{
36c14ed9 1431 int i, err, count, nents, offset;
7fc3cdab
MW		 1432 struct scatterlist *sg;
1433 struct page **pages;
eca18b23 1434 struct nvme_iod *iod;
36c14ed9
MW		 1435
1436 if (addr & 3)
eca18b23 1437 return ERR_PTR(-EINVAL);
5460fc03 1438 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1439 return ERR_PTR(-EINVAL);
7fc3cdab 1440
36c14ed9 1441 offset = offset_in_page(addr);
7fc3cdab
MW		 1442 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1443 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1444 if (!pages)
1445 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1446
1447 err = get_user_pages_fast(addr, count, 1, pages);
1448 if (err < count) {
1449 count = err;
1450 err = -EFAULT;
1451 goto put_pages;
1452 }
7fc3cdab 1453
eca18b23
MW		 1454 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1455 sg = iod->sg;
36c14ed9 1456 sg_init_table(sg, count);
d0ba1e49
MW		 1457 for (i = 0; i < count; i++) {
1458 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1459 min_t(unsigned, length, PAGE_SIZE - offset),
1460 offset);
d0ba1e49
MW		 1461 length -= (PAGE_SIZE - offset);
1462 offset = 0;
7fc3cdab 1463 }
fe304c43 1464 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1465 iod->nents = count;
7fc3cdab
MW		 1466
1467 err = -ENOMEM;
1468 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1469 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1470 if (!nents)
eca18b23 1471 goto free_iod;
b60503ba 1472
7fc3cdab 1473 kfree(pages);
eca18b23 1474 return iod;
b60503ba 1475
eca18b23
MW		 1476 free_iod:
1477 kfree(iod);
7fc3cdab
MW		 1478 put_pages:
1479 for (i = 0; i < count; i++)
1480 put_page(pages[i]);
1481 kfree(pages);
eca18b23 1482 return ERR_PTR(err);
7fc3cdab 1483}
b60503ba 1484
5d0f6131 1485void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1486 struct nvme_iod *iod)
7fc3cdab 1487{
1c2ad9fa 1488 int i;
b60503ba 1489
1c2ad9fa
MW		 1490 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1491 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1492
1c2ad9fa
MW		 1493 for (i = 0; i < iod->nents; i++)
1494 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1495}
b60503ba 1496
a53295b6
MW		 1497static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1498{
1499 struct nvme_dev *dev = ns->dev;
1500 struct nvme_queue *nvmeq;
1501 struct nvme_user_io io;
1502 struct nvme_command c;
f410c680
KB		 1503 unsigned length, meta_len;
1504 int status, i;
1505 struct nvme_iod *iod, *meta_iod = NULL;
1506 dma_addr_t meta_dma_addr;
1507 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1508
1509 if (copy_from_user(&io, uio, sizeof(io)))
1510 return -EFAULT;
6c7d4945 1511 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1512 meta_len = (io.nblocks + 1) * ns->ms;
1513
1514 if (meta_len && ((io.metadata & 3) || !io.metadata))
1515 return -EINVAL;
6c7d4945
MW		 1516
1517 switch (io.opcode) {
1518 case nvme_cmd_write:
1519 case nvme_cmd_read:
6bbf1acd 1520 case nvme_cmd_compare:
eca18b23 1521 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1522 break;
6c7d4945 1523 default:
6bbf1acd 1524 return -EINVAL;
6c7d4945
MW		 1525 }
1526
eca18b23
MW		 1527 if (IS_ERR(iod))
1528 return PTR_ERR(iod);
a53295b6
MW		 1529
1530 memset(&c, 0, sizeof(c));
1531 c.rw.opcode = io.opcode;
1532 c.rw.flags = io.flags;
6c7d4945 1533 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1534 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1535 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1536 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1537 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1538 c.rw.reftag = cpu_to_le32(io.reftag);
1539 c.rw.apptag = cpu_to_le16(io.apptag);
1540 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1541
1542 if (meta_len) {
1b56749e
KB		 1543 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1544 meta_len);
f410c680
KB		 1545 if (IS_ERR(meta_iod)) {
1546 status = PTR_ERR(meta_iod);
1547 meta_iod = NULL;
1548 goto unmap;
1549 }
1550
1551 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1552 &meta_dma_addr, GFP_KERNEL);
1553 if (!meta_mem) {
1554 status = -ENOMEM;
1555 goto unmap;
1556 }
1557
1558 if (io.opcode & 1) {
1559 int meta_offset = 0;
1560
1561 for (i = 0; i < meta_iod->nents; i++) {
1562 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1563 meta_iod->sg[i].offset;
1564 memcpy(meta_mem + meta_offset, meta,
1565 meta_iod->sg[i].length);
1566 kunmap_atomic(meta);
1567 meta_offset += meta_iod->sg[i].length;
1568 }
1569 }
1570
1571 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1572 }
1573
eca18b23 1574 length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
a53295b6 1575
040a93b5 1576 nvmeq = get_nvmeq(dev);
fa922821
MW		 1577 /*
1578 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
b1ad37ef
MW		 1579 * disabled. We may be preempted at any point, and be rescheduled
1580 * to a different CPU. That will cause cacheline bouncing, but no
1581 * additional races since q_lock already protects against other CPUs.
1582 */
a53295b6 1583 put_nvmeq(nvmeq);
b77954cb
MW		 1584 if (length != (io.nblocks + 1) << ns->lba_shift)
1585 status = -ENOMEM;
22404274
KB		 1586 else if (!nvmeq || nvmeq->q_suspended)
1587 status = -EBUSY;
b77954cb 1588 else
ff976d72 1589 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
a53295b6 1590
f410c680
KB		 1591 if (meta_len) {
1592 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1593 int meta_offset = 0;
1594
1595 for (i = 0; i < meta_iod->nents; i++) {
1596 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1597 meta_iod->sg[i].offset;
1598 memcpy(meta, meta_mem + meta_offset,
1599 meta_iod->sg[i].length);
1600 kunmap_atomic(meta);
1601 meta_offset += meta_iod->sg[i].length;
1602 }
1603 }
1604
1605 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1606 meta_dma_addr);
1607 }
1608
1609 unmap:
1c2ad9fa 1610 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1611 nvme_free_iod(dev, iod);
f410c680
KB		 1612
1613 if (meta_iod) {
1614 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1615 nvme_free_iod(dev, meta_iod);
1616 }
1617
a53295b6
MW		 1618 return status;
1619}
1620
50af8bae 1621static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1622 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1623{
6bbf1acd 1624 struct nvme_admin_cmd cmd;
6ee44cdc 1625 struct nvme_command c;
eca18b23 1626 int status, length;
c7d36ab8 1627 struct nvme_iod *uninitialized_var(iod);
94f370ca 1628 unsigned timeout;
6ee44cdc 1629
6bbf1acd
MW		 1630 if (!capable(CAP_SYS_ADMIN))
1631 return -EACCES;
1632 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1633 return -EFAULT;
6ee44cdc
MW		 1634
1635 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1636 c.common.opcode = cmd.opcode;
1637 c.common.flags = cmd.flags;
1638 c.common.nsid = cpu_to_le32(cmd.nsid);
1639 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1640 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1641 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1642 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1643 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1644 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1645 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1646 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1647
1648 length = cmd.data_len;
1649 if (cmd.data_len) {
49742188
MW		 1650 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1651 length);
eca18b23
MW		 1652 if (IS_ERR(iod))
1653 return PTR_ERR(iod);
1654 length = nvme_setup_prps(dev, &c.common, iod, length,
1655 GFP_KERNEL);
6bbf1acd
MW		 1656 }
1657
94f370ca
KB		 1658 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1659 ADMIN_TIMEOUT;
6bbf1acd 1660 if (length != cmd.data_len)
b77954cb
MW		 1661 status = -ENOMEM;
1662 else
94f370ca
KB		 1663 status = nvme_submit_sync_cmd(dev->queues[0], &c, &cmd.result,
1664 timeout);
eca18b23 1665
6bbf1acd 1666 if (cmd.data_len) {
1c2ad9fa 1667 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1668 nvme_free_iod(dev, iod);
6bbf1acd 1669 }
f4f117f6 1670
cf90bc48 1671 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1672 sizeof(cmd.result)))
1673 status = -EFAULT;
1674
6ee44cdc
MW		 1675 return status;
1676}
1677
b60503ba
MW		 1678static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1679 unsigned long arg)
1680{
1681 struct nvme_ns *ns = bdev->bd_disk->private_data;
1682
1683 switch (cmd) {
6bbf1acd 1684 case NVME_IOCTL_ID:
c3bfe717 1685 force_successful_syscall_return();
6bbf1acd
MW		 1686 return ns->ns_id;
1687 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1688 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW		 1689 case NVME_IOCTL_SUBMIT_IO:
1690 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1691 case SG_GET_VERSION_NUM:
1692 return nvme_sg_get_version_num((void __user *)arg);
1693 case SG_IO:
1694 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1695 default:
1696 return -ENOTTY;
1697 }
1698}
1699
320a3827
KB		 1700#ifdef CONFIG_COMPAT
1701static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1702 unsigned int cmd, unsigned long arg)
1703{
1704 struct nvme_ns *ns = bdev->bd_disk->private_data;
1705
1706 switch (cmd) {
1707 case SG_IO:
1708 return nvme_sg_io32(ns, arg);
1709 }
1710 return nvme_ioctl(bdev, mode, cmd, arg);
1711}
1712#else
1713#define nvme_compat_ioctl NULL
1714#endif
1715
b60503ba
MW		 1716static const struct block_device_operations nvme_fops = {
1717 .owner = THIS_MODULE,
1718 .ioctl = nvme_ioctl,
320a3827 1719 .compat_ioctl = nvme_compat_ioctl,
b60503ba
MW		 1720};
1721
1fa6aead
MW		 1722static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1723{
1724 while (bio_list_peek(&nvmeq->sq_cong)) {
1725 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1726 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
427e9708
KB		 1727
1728 if (bio_list_empty(&nvmeq->sq_cong))
1729 remove_wait_queue(&nvmeq->sq_full,
1730 &nvmeq->sq_cong_wait);
1fa6aead 1731 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
427e9708
KB		 1732 if (bio_list_empty(&nvmeq->sq_cong))
1733 add_wait_queue(&nvmeq->sq_full,
1734 &nvmeq->sq_cong_wait);
1fa6aead
MW		 1735 bio_list_add_head(&nvmeq->sq_cong, bio);
1736 break;
1737 }
1738 }
1739}
1740
1741static int nvme_kthread(void *data)
1742{
d4b4ff8e 1743 struct nvme_dev *dev, *next;
1fa6aead
MW		 1744
1745 while (!kthread_should_stop()) {
564a232c 1746 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1747 spin_lock(&dev_list_lock);
d4b4ff8e 1748 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1749 int i;
d4b4ff8e
KB		 1750 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1751 dev->initialized) {
1752 if (work_busy(&dev->reset_work))
1753 continue;
1754 list_del_init(&dev->node);
1755 dev_warn(&dev->pci_dev->dev,
1756 "Failed status, reset controller\n");
1757 INIT_WORK(&dev->reset_work,
1758 nvme_reset_failed_dev);
1759 queue_work(nvme_workq, &dev->reset_work);
1760 continue;
1761 }
1fa6aead
MW		 1762 for (i = 0; i < dev->queue_count; i++) {
1763 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 1764 if (!nvmeq)
1765 continue;
1fa6aead 1766 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1767 if (nvmeq->q_suspended)
1768 goto unlock;
bc57a0f7 1769 nvme_process_cq(nvmeq);
a09115b2 1770 nvme_cancel_ios(nvmeq, true);
1fa6aead 1771 nvme_resubmit_bios(nvmeq);
22404274 1772 unlock:
1fa6aead
MW		 1773 spin_unlock_irq(&nvmeq->q_lock);
1774 }
1775 }
1776 spin_unlock(&dev_list_lock);
acb7aa0d 1777 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1778 }
1779 return 0;
1780}
1781
0e5e4f0e
KB		 1782static void nvme_config_discard(struct nvme_ns *ns)
1783{
1784 u32 logical_block_size = queue_logical_block_size(ns->queue);
1785 ns->queue->limits.discard_zeroes_data = 0;
1786 ns->queue->limits.discard_alignment = logical_block_size;
1787 ns->queue->limits.discard_granularity = logical_block_size;
1788 ns->queue->limits.max_discard_sectors = 0xffffffff;
1789 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1790}
1791
c3bfe717 1792static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1793 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1794{
1795 struct nvme_ns *ns;
1796 struct gendisk *disk;
1797 int lbaf;
1798
1799 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1800 return NULL;
1801
1802 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1803 if (!ns)
1804 return NULL;
1805 ns->queue = blk_alloc_queue(GFP_KERNEL);
1806 if (!ns->queue)
1807 goto out_free_ns;
4eeb9215
MW		 1808 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1809 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1810 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 1811 blk_queue_make_request(ns->queue, nvme_make_request);
1812 ns->dev = dev;
1813 ns->queue->queuedata = ns;
1814
469071a3 1815 disk = alloc_disk(0);
b60503ba
MW		 1816 if (!disk)
1817 goto out_free_queue;
5aff9382 1818 ns->ns_id = nsid;
b60503ba
MW		 1819 ns->disk = disk;
1820 lbaf = id->flbas & 0xf;
1821 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1822 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1823 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1824 if (dev->max_hw_sectors)
1825 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
b60503ba
MW		 1826
1827 disk->major = nvme_major;
469071a3 1828 disk->first_minor = 0;
b60503ba
MW		 1829 disk->fops = &nvme_fops;
1830 disk->private_data = ns;
1831 disk->queue = ns->queue;
388f037f 1832 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1833 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1834 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1835 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1836
0e5e4f0e
KB		 1837 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1838 nvme_config_discard(ns);
1839
b60503ba
MW		 1840 return ns;
1841
1842 out_free_queue:
1843 blk_cleanup_queue(ns->queue);
1844 out_free_ns:
1845 kfree(ns);
1846 return NULL;
1847}
1848
1849static void nvme_ns_free(struct nvme_ns *ns)
1850{
1851 put_disk(ns->disk);
1852 blk_cleanup_queue(ns->queue);
1853 kfree(ns);
1854}
1855
b3b06812 1856static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 1857{
1858 int status;
1859 u32 result;
b3b06812 1860 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 1861
df348139 1862 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 1863 &result);
b60503ba 1864 if (status)
7e03b124 1865 return status < 0 ? -EIO : -EBUSY;
b60503ba
MW		 1866 return min(result & 0xffff, result >> 16) + 1;
1867}
1868
9d713c2b
KB		 1869static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1870{
b80d5ccc 1871 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 1872}
1873
8d85fce7 1874static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1875{
fa08a396 1876 struct pci_dev *pdev = dev->pci_dev;
9d713c2b 1877 int result, cpu, i, vecs, nr_io_queues, size, q_depth;
b60503ba 1878
b348b7d5
MW		 1879 nr_io_queues = num_online_cpus();
1880 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW		 1881 if (result < 0)
1882 return result;
b348b7d5
MW		 1883 if (result < nr_io_queues)
1884 nr_io_queues = result;
b60503ba 1885
9d713c2b
KB		 1886 size = db_bar_size(dev, nr_io_queues);
1887 if (size > 8192) {
f1938f6e 1888 iounmap(dev->bar);
9d713c2b
KB		 1889 do {
1890 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1891 if (dev->bar)
1892 break;
1893 if (!--nr_io_queues)
1894 return -ENOMEM;
1895 size = db_bar_size(dev, nr_io_queues);
1896 } while (1);
f1938f6e
MW		 1897 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1898 dev->queues[0]->q_db = dev->dbs;
1899 }
1900
9d713c2b
KB		 1901 /* Deregister the admin queue's interrupt */
1902 free_irq(dev->entry[0].vector, dev->queues[0]);
1903
063a8096
MW		 1904 vecs = nr_io_queues;
1905 for (i = 0; i < vecs; i++)
1b23484b
MW		 1906 dev->entry[i].entry = i;
1907 for (;;) {
063a8096
MW		 1908 result = pci_enable_msix(pdev, dev->entry, vecs);
1909 if (result <= 0)
1b23484b 1910 break;
063a8096 1911 vecs = result;
1b23484b
MW		 1912 }
1913
063a8096
MW		 1914 if (result < 0) {
1915 vecs = nr_io_queues;
1916 if (vecs > 32)
1917 vecs = 32;
fa08a396 1918 for (;;) {
063a8096 1919 result = pci_enable_msi_block(pdev, vecs);
fa08a396 1920 if (result == 0) {
063a8096 1921 for (i = 0; i < vecs; i++)
fa08a396
RRG		 1922 dev->entry[i].vector = i + pdev->irq;
1923 break;
063a8096
MW		 1924 } else if (result < 0) {
1925 vecs = 1;
fa08a396
RRG		 1926 break;
1927 }
063a8096 1928 vecs = result;
fa08a396
RRG		 1929 }
1930 }
1931
063a8096
MW		 1932 /*
1933 * Should investigate if there's a performance win from allocating
1934 * more queues than interrupt vectors; it might allow the submission
1935 * path to scale better, even if the receive path is limited by the
1936 * number of interrupts.
1937 */
1938 nr_io_queues = vecs;
1939
1b23484b 1940 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
9d713c2b
KB		 1941 if (result) {
1942 dev->queues[0]->q_suspended = 1;
22404274 1943 goto free_queues;
9d713c2b 1944 }
1b23484b 1945
cd638946
KB		 1946 /* Free previously allocated queues that are no longer usable */
1947 spin_lock(&dev_list_lock);
1948 for (i = dev->queue_count - 1; i > nr_io_queues; i--) {
1949 struct nvme_queue *nvmeq = dev->queues[i];
1950
0a8d44cb 1951 spin_lock_irq(&nvmeq->q_lock);
cd638946 1952 nvme_cancel_ios(nvmeq, false);
0a8d44cb 1953 spin_unlock_irq(&nvmeq->q_lock);
cd638946
KB		 1954
1955 nvme_free_queue(nvmeq);
1956 dev->queue_count--;
1957 dev->queues[i] = NULL;
1958 }
1959 spin_unlock(&dev_list_lock);
1960
1b23484b 1961 cpu = cpumask_first(cpu_online_mask);
b348b7d5 1962 for (i = 0; i < nr_io_queues; i++) {
1b23484b
MW		 1963 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1964 cpu = cpumask_next(cpu, cpu_online_mask);
1965 }
1966
a0cadb85
KB		 1967 q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1,
1968 NVME_Q_DEPTH);
cd638946 1969 for (i = dev->queue_count - 1; i < nr_io_queues; i++) {
22404274
KB		 1970 dev->queues[i + 1] = nvme_alloc_queue(dev, i + 1, q_depth, i);
1971 if (!dev->queues[i + 1]) {
1972 result = -ENOMEM;
1973 goto free_queues;
1974 }
1b23484b 1975 }
b60503ba 1976
9ecdc946
MW		 1977 for (; i < num_possible_cpus(); i++) {
1978 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1979 dev->queues[i + 1] = dev->queues[target + 1];
1980 }
1981
22404274
KB		 1982 for (i = 1; i < dev->queue_count; i++) {
1983 result = nvme_create_queue(dev->queues[i], i);
1984 if (result) {
1985 for (--i; i > 0; i--)
1986 nvme_disable_queue(dev, i);
1987 goto free_queues;
1988 }
1989 }
b60503ba 1990
22404274 1991 return 0;
b60503ba 1992
22404274 1993 free_queues:
a1a5ef99 1994 nvme_free_queues(dev, 1);
22404274 1995 return result;
b60503ba
MW		 1996}
1997
422ef0c7
MW		 1998/*
1999 * Return: error value if an error occurred setting up the queues or calling
2000 * Identify Device. 0 if these succeeded, even if adding some of the
2001 * namespaces failed. At the moment, these failures are silent. TBD which
2002 * failures should be reported.
2003 */
8d85fce7 2004static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2005{
68608c26 2006 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2007 int res;
2008 unsigned nn, i;
cbb6218f 2009 struct nvme_ns *ns;
51814232 2010 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2011 struct nvme_id_ns *id_ns;
2012 void *mem;
b60503ba 2013 dma_addr_t dma_addr;
159b67d7 2014 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2015
68608c26 2016 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2017 if (!mem)
2018 return -ENOMEM;
b60503ba 2019
bc5fc7e4 2020 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba
MW		 2021 if (res) {
2022 res = -EIO;
cbb6218f 2023 goto out;
b60503ba
MW		 2024 }
2025
bc5fc7e4 2026 ctrl = mem;
51814232 2027 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2028 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2029 dev->abort_limit = ctrl->acl + 1;
51814232
MW		 2030 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2031 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2032 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2033 if (ctrl->mdts)
8fc23e03 2034 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26
MW		 2035 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2036 (pdev->device == 0x0953) && ctrl->vs[3])
159b67d7 2037 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
b60503ba 2038
bc5fc7e4 2039 id_ns = mem;
2b2c1896 2040 for (i = 1; i <= nn; i++) {
bc5fc7e4 2041 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2042 if (res)
2043 continue;
2044
bc5fc7e4 2045 if (id_ns->ncap == 0)
b60503ba
MW		 2046 continue;
2047
bc5fc7e4 2048 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2049 dma_addr + 4096, NULL);
b60503ba 2050 if (res)
12209036 2051 memset(mem + 4096, 0, 4096);
b60503ba 2052
bc5fc7e4 2053 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2054 if (ns)
2055 list_add_tail(&ns->list, &dev->namespaces);
2056 }
2057 list_for_each_entry(ns, &dev->namespaces, list)
2058 add_disk(ns->disk);
422ef0c7 2059 res = 0;
b60503ba 2060
bc5fc7e4 2061 out:
684f5c20 2062 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2063 return res;
2064}
2065
0877cb0d
KB		 2066static int nvme_dev_map(struct nvme_dev *dev)
2067{
2068 int bars, result = -ENOMEM;
2069 struct pci_dev *pdev = dev->pci_dev;
2070
2071 if (pci_enable_device_mem(pdev))
2072 return result;
2073
2074 dev->entry[0].vector = pdev->irq;
2075 pci_set_master(pdev);
2076 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2077 if (pci_request_selected_regions(pdev, bars, "nvme"))
2078 goto disable_pci;
2079
052d0efa
RK		 2080 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2081 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2082 goto disable;
0877cb0d 2083
0877cb0d
KB		 2084 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2085 if (!dev->bar)
2086 goto disable;
0e53d180
KB		 2087 if (readl(&dev->bar->csts) == -1) {
2088 result = -ENODEV;
2089 goto unmap;
2090 }
b80d5ccc 2091 dev->db_stride = 1 << NVME_CAP_STRIDE(readq(&dev->bar->cap));
0877cb0d
KB		 2092 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2093
2094 return 0;
2095
0e53d180
KB		 2096 unmap:
2097 iounmap(dev->bar);
2098 dev->bar = NULL;
0877cb0d
KB		 2099 disable:
2100 pci_release_regions(pdev);
2101 disable_pci:
2102 pci_disable_device(pdev);
2103 return result;
2104}
2105
2106static void nvme_dev_unmap(struct nvme_dev *dev)
2107{
2108 if (dev->pci_dev->msi_enabled)
2109 pci_disable_msi(dev->pci_dev);
2110 else if (dev->pci_dev->msix_enabled)
2111 pci_disable_msix(dev->pci_dev);
2112
2113 if (dev->bar) {
2114 iounmap(dev->bar);
2115 dev->bar = NULL;
9a6b9458 2116 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2117 }
2118
0877cb0d
KB		 2119 if (pci_is_enabled(dev->pci_dev))
2120 pci_disable_device(dev->pci_dev);
2121}
2122
4d115420
KB		 2123struct nvme_delq_ctx {
2124 struct task_struct *waiter;
2125 struct kthread_worker *worker;
2126 atomic_t refcount;
2127};
2128
2129static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2130{
2131 dq->waiter = current;
2132 mb();
2133
2134 for (;;) {
2135 set_current_state(TASK_KILLABLE);
2136 if (!atomic_read(&dq->refcount))
2137 break;
2138 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2139 fatal_signal_pending(current)) {
2140 set_current_state(TASK_RUNNING);
2141
2142 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2143 nvme_disable_queue(dev, 0);
2144
2145 send_sig(SIGKILL, dq->worker->task, 1);
2146 flush_kthread_worker(dq->worker);
2147 return;
2148 }
2149 }
2150 set_current_state(TASK_RUNNING);
2151}
2152
2153static void nvme_put_dq(struct nvme_delq_ctx *dq)
2154{
2155 atomic_dec(&dq->refcount);
2156 if (dq->waiter)
2157 wake_up_process(dq->waiter);
2158}
2159
2160static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2161{
2162 atomic_inc(&dq->refcount);
2163 return dq;
2164}
2165
2166static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2167{
2168 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2169
2170 nvme_clear_queue(nvmeq);
2171 nvme_put_dq(dq);
2172}
2173
2174static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2175 kthread_work_func_t fn)
2176{
2177 struct nvme_command c;
2178
2179 memset(&c, 0, sizeof(c));
2180 c.delete_queue.opcode = opcode;
2181 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2182
2183 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2184 return nvme_submit_admin_cmd_async(nvmeq->dev, &c, &nvmeq->cmdinfo);
2185}
2186
2187static void nvme_del_cq_work_handler(struct kthread_work *work)
2188{
2189 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2190 cmdinfo.work);
2191 nvme_del_queue_end(nvmeq);
2192}
2193
2194static int nvme_delete_cq(struct nvme_queue *nvmeq)
2195{
2196 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2197 nvme_del_cq_work_handler);
2198}
2199
2200static void nvme_del_sq_work_handler(struct kthread_work *work)
2201{
2202 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2203 cmdinfo.work);
2204 int status = nvmeq->cmdinfo.status;
2205
2206 if (!status)
2207 status = nvme_delete_cq(nvmeq);
2208 if (status)
2209 nvme_del_queue_end(nvmeq);
2210}
2211
2212static int nvme_delete_sq(struct nvme_queue *nvmeq)
2213{
2214 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2215 nvme_del_sq_work_handler);
2216}
2217
2218static void nvme_del_queue_start(struct kthread_work *work)
2219{
2220 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2221 cmdinfo.work);
2222 allow_signal(SIGKILL);
2223 if (nvme_delete_sq(nvmeq))
2224 nvme_del_queue_end(nvmeq);
2225}
2226
2227static void nvme_disable_io_queues(struct nvme_dev *dev)
2228{
2229 int i;
2230 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2231 struct nvme_delq_ctx dq;
2232 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2233 &worker, "nvme%d", dev->instance);
2234
2235 if (IS_ERR(kworker_task)) {
2236 dev_err(&dev->pci_dev->dev,
2237 "Failed to create queue del task\n");
2238 for (i = dev->queue_count - 1; i > 0; i--)
2239 nvme_disable_queue(dev, i);
2240 return;
2241 }
2242
2243 dq.waiter = NULL;
2244 atomic_set(&dq.refcount, 0);
2245 dq.worker = &worker;
2246 for (i = dev->queue_count - 1; i > 0; i--) {
2247 struct nvme_queue *nvmeq = dev->queues[i];
2248
2249 if (nvme_suspend_queue(nvmeq))
2250 continue;
2251 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2252 nvmeq->cmdinfo.worker = dq.worker;
2253 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2254 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2255 }
2256 nvme_wait_dq(&dq, dev);
2257 kthread_stop(kworker_task);
2258}
2259
f0b50732 2260static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2261{
22404274
KB		 2262 int i;
2263
d4b4ff8e 2264 dev->initialized = 0;
b60503ba 2265
1fa6aead 2266 spin_lock(&dev_list_lock);
f0b50732 2267 list_del_init(&dev->node);
1fa6aead
MW		 2268 spin_unlock(&dev_list_lock);
2269
4d115420
KB		 2270 if (!dev->bar || (dev->bar && readl(&dev->bar->csts) == -1)) {
2271 for (i = dev->queue_count - 1; i >= 0; i--) {
2272 struct nvme_queue *nvmeq = dev->queues[i];
2273 nvme_suspend_queue(nvmeq);
2274 nvme_clear_queue(nvmeq);
2275 }
2276 } else {
2277 nvme_disable_io_queues(dev);
1894d8f1 2278 nvme_shutdown_ctrl(dev);
4d115420
KB		 2279 nvme_disable_queue(dev, 0);
2280 }
f0b50732
KB		 2281 nvme_dev_unmap(dev);
2282}
2283
2284static void nvme_dev_remove(struct nvme_dev *dev)
2285{
2286 struct nvme_ns *ns, *next;
2287
b60503ba
MW		 2288 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2289 list_del(&ns->list);
2290 del_gendisk(ns->disk);
2291 nvme_ns_free(ns);
2292 }
b60503ba
MW		 2293}
2294
091b6092
MW		 2295static int nvme_setup_prp_pools(struct nvme_dev *dev)
2296{
2297 struct device *dmadev = &dev->pci_dev->dev;
2298 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2299 PAGE_SIZE, PAGE_SIZE, 0);
2300 if (!dev->prp_page_pool)
2301 return -ENOMEM;
2302
99802a7a
MW		 2303 /* Optimisation for I/Os between 4k and 128k */
2304 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2305 256, 256, 0);
2306 if (!dev->prp_small_pool) {
2307 dma_pool_destroy(dev->prp_page_pool);
2308 return -ENOMEM;
2309 }
091b6092
MW		 2310 return 0;
2311}
2312
2313static void nvme_release_prp_pools(struct nvme_dev *dev)
2314{
2315 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2316 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2317}
2318
cd58ad7d
QSA		 2319static DEFINE_IDA(nvme_instance_ida);
2320
2321static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2322{
cd58ad7d
QSA		 2323 int instance, error;
2324
2325 do {
2326 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2327 return -ENODEV;
2328
2329 spin_lock(&dev_list_lock);
2330 error = ida_get_new(&nvme_instance_ida, &instance);
2331 spin_unlock(&dev_list_lock);
2332 } while (error == -EAGAIN);
2333
2334 if (error)
2335 return -ENODEV;
2336
2337 dev->instance = instance;
2338 return 0;
b60503ba
MW		 2339}
2340
2341static void nvme_release_instance(struct nvme_dev *dev)
2342{
cd58ad7d
QSA		 2343 spin_lock(&dev_list_lock);
2344 ida_remove(&nvme_instance_ida, dev->instance);
2345 spin_unlock(&dev_list_lock);
b60503ba
MW		 2346}
2347
5e82e952
KB		 2348static void nvme_free_dev(struct kref *kref)
2349{
2350 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
5e82e952
KB		 2351 kfree(dev->queues);
2352 kfree(dev->entry);
2353 kfree(dev);
2354}
2355
2356static int nvme_dev_open(struct inode *inode, struct file *f)
2357{
2358 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2359 miscdev);
2360 kref_get(&dev->kref);
2361 f->private_data = dev;
2362 return 0;
2363}
2364
2365static int nvme_dev_release(struct inode *inode, struct file *f)
2366{
2367 struct nvme_dev *dev = f->private_data;
2368 kref_put(&dev->kref, nvme_free_dev);
2369 return 0;
2370}
2371
2372static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2373{
2374 struct nvme_dev *dev = f->private_data;
2375 switch (cmd) {
2376 case NVME_IOCTL_ADMIN_CMD:
2377 return nvme_user_admin_cmd(dev, (void __user *)arg);
2378 default:
2379 return -ENOTTY;
2380 }
2381}
2382
2383static const struct file_operations nvme_dev_fops = {
2384 .owner = THIS_MODULE,
2385 .open = nvme_dev_open,
2386 .release = nvme_dev_release,
2387 .unlocked_ioctl = nvme_dev_ioctl,
2388 .compat_ioctl = nvme_dev_ioctl,
2389};
2390
f0b50732
KB		 2391static int nvme_dev_start(struct nvme_dev *dev)
2392{
2393 int result;
2394
2395 result = nvme_dev_map(dev);
2396 if (result)
2397 return result;
2398
2399 result = nvme_configure_admin_queue(dev);
2400 if (result)
2401 goto unmap;
2402
2403 spin_lock(&dev_list_lock);
2404 list_add(&dev->node, &dev_list);
2405 spin_unlock(&dev_list_lock);
2406
2407 result = nvme_setup_io_queues(dev);
d82e8bfd 2408 if (result && result != -EBUSY)
f0b50732
KB		 2409 goto disable;
2410
d82e8bfd 2411 return result;
f0b50732
KB		 2412
2413 disable:
a1a5ef99 2414 nvme_disable_queue(dev, 0);
f0b50732
KB		 2415 spin_lock(&dev_list_lock);
2416 list_del_init(&dev->node);
2417 spin_unlock(&dev_list_lock);
2418 unmap:
2419 nvme_dev_unmap(dev);
2420 return result;
2421}
2422
9a6b9458
KB		 2423static int nvme_remove_dead_ctrl(void *arg)
2424{
2425 struct nvme_dev *dev = (struct nvme_dev *)arg;
2426 struct pci_dev *pdev = dev->pci_dev;
2427
2428 if (pci_get_drvdata(pdev))
2429 pci_stop_and_remove_bus_device(pdev);
2430 kref_put(&dev->kref, nvme_free_dev);
2431 return 0;
2432}
2433
2434static void nvme_remove_disks(struct work_struct *ws)
2435{
2436 int i;
2437 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2438
2439 nvme_dev_remove(dev);
2440 spin_lock(&dev_list_lock);
2441 for (i = dev->queue_count - 1; i > 0; i--) {
2442 BUG_ON(!dev->queues[i] || !dev->queues[i]->q_suspended);
2443 nvme_free_queue(dev->queues[i]);
2444 dev->queue_count--;
2445 dev->queues[i] = NULL;
2446 }
2447 spin_unlock(&dev_list_lock);
2448}
2449
2450static int nvme_dev_resume(struct nvme_dev *dev)
2451{
2452 int ret;
2453
2454 ret = nvme_dev_start(dev);
2455 if (ret && ret != -EBUSY)
2456 return ret;
2457 if (ret == -EBUSY) {
2458 spin_lock(&dev_list_lock);
2459 INIT_WORK(&dev->reset_work, nvme_remove_disks);
2460 queue_work(nvme_workq, &dev->reset_work);
2461 spin_unlock(&dev_list_lock);
2462 }
d4b4ff8e 2463 dev->initialized = 1;
9a6b9458
KB		 2464 return 0;
2465}
2466
2467static void nvme_dev_reset(struct nvme_dev *dev)
2468{
2469 nvme_dev_shutdown(dev);
2470 if (nvme_dev_resume(dev)) {
2471 dev_err(&dev->pci_dev->dev, "Device failed to resume\n");
2472 kref_get(&dev->kref);
2473 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2474 dev->instance))) {
2475 dev_err(&dev->pci_dev->dev,
2476 "Failed to start controller remove task\n");
2477 kref_put(&dev->kref, nvme_free_dev);
2478 }
2479 }
2480}
2481
2482static void nvme_reset_failed_dev(struct work_struct *ws)
2483{
2484 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2485 nvme_dev_reset(dev);
2486}
2487
8d85fce7 2488static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2489{
0877cb0d 2490 int result = -ENOMEM;
b60503ba
MW		 2491 struct nvme_dev *dev;
2492
2493 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2494 if (!dev)
2495 return -ENOMEM;
2496 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2497 GFP_KERNEL);
2498 if (!dev->entry)
2499 goto free;
1b23484b
MW		 2500 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2501 GFP_KERNEL);
b60503ba
MW		 2502 if (!dev->queues)
2503 goto free;
2504
2505 INIT_LIST_HEAD(&dev->namespaces);
2506 dev->pci_dev = pdev;
9a6b9458 2507 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2508 result = nvme_set_instance(dev);
2509 if (result)
0877cb0d 2510 goto free;
b60503ba 2511
091b6092
MW		 2512 result = nvme_setup_prp_pools(dev);
2513 if (result)
0877cb0d 2514 goto release;
091b6092 2515
f0b50732 2516 result = nvme_dev_start(dev);
d82e8bfd
KB		 2517 if (result) {
2518 if (result == -EBUSY)
2519 goto create_cdev;
0877cb0d 2520 goto release_pools;
d82e8bfd 2521 }
b60503ba 2522
740216fc 2523 result = nvme_dev_add(dev);
d82e8bfd 2524 if (result)
f0b50732 2525 goto shutdown;
740216fc 2526
d82e8bfd 2527 create_cdev:
5e82e952
KB		 2528 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2529 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2530 dev->miscdev.parent = &pdev->dev;
2531 dev->miscdev.name = dev->name;
2532 dev->miscdev.fops = &nvme_dev_fops;
2533 result = misc_register(&dev->miscdev);
2534 if (result)
2535 goto remove;
2536
d4b4ff8e 2537 dev->initialized = 1;
5e82e952 2538 kref_init(&dev->kref);
b60503ba
MW		 2539 return 0;
2540
5e82e952
KB		 2541 remove:
2542 nvme_dev_remove(dev);
f0b50732
KB		 2543 shutdown:
2544 nvme_dev_shutdown(dev);
0877cb0d 2545 release_pools:
a1a5ef99 2546 nvme_free_queues(dev, 0);
091b6092 2547 nvme_release_prp_pools(dev);
0877cb0d
KB		 2548 release:
2549 nvme_release_instance(dev);
b60503ba
MW		 2550 free:
2551 kfree(dev->queues);
2552 kfree(dev->entry);
2553 kfree(dev);
2554 return result;
2555}
2556
09ece142
KB		 2557static void nvme_shutdown(struct pci_dev *pdev)
2558{
2559 struct nvme_dev *dev = pci_get_drvdata(pdev);
2560 nvme_dev_shutdown(dev);
2561}
2562
8d85fce7 2563static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2564{
2565 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2566
2567 spin_lock(&dev_list_lock);
2568 list_del_init(&dev->node);
2569 spin_unlock(&dev_list_lock);
2570
2571 pci_set_drvdata(pdev, NULL);
2572 flush_work(&dev->reset_work);
5e82e952 2573 misc_deregister(&dev->miscdev);
9a6b9458
KB		 2574 nvme_dev_remove(dev);
2575 nvme_dev_shutdown(dev);
a1a5ef99 2576 nvme_free_queues(dev, 0);
9a6b9458
KB		 2577 nvme_release_instance(dev);
2578 nvme_release_prp_pools(dev);
5e82e952 2579 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2580}
2581
2582/* These functions are yet to be implemented */
2583#define nvme_error_detected NULL
2584#define nvme_dump_registers NULL
2585#define nvme_link_reset NULL
2586#define nvme_slot_reset NULL
2587#define nvme_error_resume NULL
cd638946
KB		 2588
2589static int nvme_suspend(struct device *dev)
2590{
2591 struct pci_dev *pdev = to_pci_dev(dev);
2592 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2593
2594 nvme_dev_shutdown(ndev);
2595 return 0;
2596}
2597
2598static int nvme_resume(struct device *dev)
2599{
2600 struct pci_dev *pdev = to_pci_dev(dev);
2601 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2602
9a6b9458
KB		 2603 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
2604 INIT_WORK(&ndev->reset_work, nvme_reset_failed_dev);
2605 queue_work(nvme_workq, &ndev->reset_work);
2606 }
2607 return 0;
cd638946
KB		 2608}
2609
2610static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2611
1d352035 2612static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2613 .error_detected = nvme_error_detected,
2614 .mmio_enabled = nvme_dump_registers,
2615 .link_reset = nvme_link_reset,
2616 .slot_reset = nvme_slot_reset,
2617 .resume = nvme_error_resume,
2618};
2619
2620/* Move to pci_ids.h later */
2621#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2622
2623static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
2624 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2625 { 0, }
2626};
2627MODULE_DEVICE_TABLE(pci, nvme_id_table);
2628
2629static struct pci_driver nvme_driver = {
2630 .name = "nvme",
2631 .id_table = nvme_id_table,
2632 .probe = nvme_probe,
8d85fce7 2633 .remove = nvme_remove,
09ece142 2634 .shutdown = nvme_shutdown,
cd638946
KB		 2635 .driver = {
2636 .pm = &nvme_dev_pm_ops,
2637 },
b60503ba
MW		 2638 .err_handler = &nvme_err_handler,
2639};
2640
2641static int __init nvme_init(void)
2642{
0ac13140 2643 int result;
1fa6aead
MW		 2644
2645 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2646 if (IS_ERR(nvme_thread))
2647 return PTR_ERR(nvme_thread);
b60503ba 2648
9a6b9458
KB		 2649 result = -ENOMEM;
2650 nvme_workq = create_singlethread_workqueue("nvme");
2651 if (!nvme_workq)
2652 goto kill_kthread;
2653
5c42ea16
KB		 2654 result = register_blkdev(nvme_major, "nvme");
2655 if (result < 0)
9a6b9458 2656 goto kill_workq;
5c42ea16 2657 else if (result > 0)
0ac13140 2658 nvme_major = result;
b60503ba
MW		 2659
2660 result = pci_register_driver(&nvme_driver);
1fa6aead
MW		 2661 if (result)
2662 goto unregister_blkdev;
2663 return 0;
b60503ba 2664
1fa6aead 2665 unregister_blkdev:
b60503ba 2666 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2667 kill_workq:
2668 destroy_workqueue(nvme_workq);
1fa6aead
MW		 2669 kill_kthread:
2670 kthread_stop(nvme_thread);
b60503ba
MW		 2671 return result;
2672}
2673
2674static void __exit nvme_exit(void)
2675{
2676 pci_unregister_driver(&nvme_driver);
2677 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2678 destroy_workqueue(nvme_workq);
1fa6aead 2679 kthread_stop(nvme_thread);
b60503ba
MW		 2680}
2681
2682MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2683MODULE_LICENSE("GPL");
366e8217 2684MODULE_VERSION("0.8");
b60503ba
MW		 2685module_init(nvme_init);
2686module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)