Commit | Line | Data |
---|---|---|
c767a54b JP |
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
2 | ||
61c4628b SS |
3 | #include <linux/errno.h> |
4 | #include <linux/kernel.h> | |
5 | #include <linux/mm.h> | |
6 | #include <linux/smp.h> | |
389d1fb1 | 7 | #include <linux/prctl.h> |
61c4628b SS |
8 | #include <linux/slab.h> |
9 | #include <linux/sched.h> | |
7f424a8b PZ |
10 | #include <linux/module.h> |
11 | #include <linux/pm.h> | |
aa276e1c | 12 | #include <linux/clockchips.h> |
9d62dcdf | 13 | #include <linux/random.h> |
7c68af6e | 14 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
15 | #include <linux/dmi.h> |
16 | #include <linux/utsname.h> | |
90e24014 RW |
17 | #include <linux/stackprotector.h> |
18 | #include <linux/tick.h> | |
19 | #include <linux/cpuidle.h> | |
61613521 | 20 | #include <trace/events/power.h> |
24f1e32c | 21 | #include <linux/hw_breakpoint.h> |
93789b32 | 22 | #include <asm/cpu.h> |
d3ec5cae | 23 | #include <asm/apic.h> |
2c1b284e | 24 | #include <asm/syscalls.h> |
389d1fb1 JF |
25 | #include <asm/idle.h> |
26 | #include <asm/uaccess.h> | |
27 | #include <asm/i387.h> | |
1361b83a | 28 | #include <asm/fpu-internal.h> |
66cb5917 | 29 | #include <asm/debugreg.h> |
90e24014 RW |
30 | #include <asm/nmi.h> |
31 | ||
45046892 TG |
32 | /* |
33 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
34 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
35 | * so they are allowed to end up in the .data..cacheline_aligned | |
36 | * section. Since TSS's are completely CPU-local, we want them | |
37 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
38 | */ | |
39 | DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS; | |
40 | ||
90e24014 RW |
41 | #ifdef CONFIG_X86_64 |
42 | static DEFINE_PER_CPU(unsigned char, is_idle); | |
43 | static ATOMIC_NOTIFIER_HEAD(idle_notifier); | |
44 | ||
45 | void idle_notifier_register(struct notifier_block *n) | |
46 | { | |
47 | atomic_notifier_chain_register(&idle_notifier, n); | |
48 | } | |
49 | EXPORT_SYMBOL_GPL(idle_notifier_register); | |
50 | ||
51 | void idle_notifier_unregister(struct notifier_block *n) | |
52 | { | |
53 | atomic_notifier_chain_unregister(&idle_notifier, n); | |
54 | } | |
55 | EXPORT_SYMBOL_GPL(idle_notifier_unregister); | |
56 | #endif | |
c1e3b377 | 57 | |
aa283f49 | 58 | struct kmem_cache *task_xstate_cachep; |
5ee481da | 59 | EXPORT_SYMBOL_GPL(task_xstate_cachep); |
61c4628b | 60 | |
55ccf3fe SS |
61 | /* |
62 | * this gets called so that we can store lazy state into memory and copy the | |
63 | * current task into the new thread. | |
64 | */ | |
61c4628b SS |
65 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
66 | { | |
86603283 AK |
67 | int ret; |
68 | ||
55ccf3fe SS |
69 | unlazy_fpu(src); |
70 | ||
61c4628b | 71 | *dst = *src; |
86603283 AK |
72 | if (fpu_allocated(&src->thread.fpu)) { |
73 | memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu)); | |
74 | ret = fpu_alloc(&dst->thread.fpu); | |
75 | if (ret) | |
76 | return ret; | |
77 | fpu_copy(&dst->thread.fpu, &src->thread.fpu); | |
aa283f49 | 78 | } |
61c4628b SS |
79 | return 0; |
80 | } | |
81 | ||
aa283f49 | 82 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 83 | { |
86603283 | 84 | fpu_free(&tsk->thread.fpu); |
aa283f49 SS |
85 | } |
86 | ||
38e7c572 | 87 | void arch_release_task_struct(struct task_struct *tsk) |
aa283f49 | 88 | { |
38e7c572 | 89 | free_thread_xstate(tsk); |
61c4628b SS |
90 | } |
91 | ||
92 | void arch_task_cache_init(void) | |
93 | { | |
94 | task_xstate_cachep = | |
95 | kmem_cache_create("task_xstate", xstate_size, | |
96 | __alignof__(union thread_xstate), | |
2dff4405 | 97 | SLAB_PANIC | SLAB_NOTRACK, NULL); |
61c4628b | 98 | } |
7f424a8b | 99 | |
389d1fb1 JF |
100 | /* |
101 | * Free current thread data structures etc.. | |
102 | */ | |
103 | void exit_thread(void) | |
104 | { | |
105 | struct task_struct *me = current; | |
106 | struct thread_struct *t = &me->thread; | |
250981e6 | 107 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 108 | |
250981e6 | 109 | if (bp) { |
389d1fb1 JF |
110 | struct tss_struct *tss = &per_cpu(init_tss, get_cpu()); |
111 | ||
389d1fb1 JF |
112 | t->io_bitmap_ptr = NULL; |
113 | clear_thread_flag(TIF_IO_BITMAP); | |
114 | /* | |
115 | * Careful, clear this in the TSS too: | |
116 | */ | |
117 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
118 | t->io_bitmap_max = 0; | |
119 | put_cpu(); | |
250981e6 | 120 | kfree(bp); |
389d1fb1 | 121 | } |
1dcc8d7b SS |
122 | |
123 | drop_fpu(me); | |
389d1fb1 JF |
124 | } |
125 | ||
814e2c84 AI |
126 | void show_regs_common(void) |
127 | { | |
84e383b3 | 128 | const char *vendor, *product, *board; |
814e2c84 | 129 | |
84e383b3 NC |
130 | vendor = dmi_get_system_info(DMI_SYS_VENDOR); |
131 | if (!vendor) | |
132 | vendor = ""; | |
a1884b8e AI |
133 | product = dmi_get_system_info(DMI_PRODUCT_NAME); |
134 | if (!product) | |
135 | product = ""; | |
814e2c84 | 136 | |
84e383b3 NC |
137 | /* Board Name is optional */ |
138 | board = dmi_get_system_info(DMI_BOARD_NAME); | |
139 | ||
c767a54b JP |
140 | printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s %s%s%s\n", |
141 | current->pid, current->comm, print_tainted(), | |
142 | init_utsname()->release, | |
143 | (int)strcspn(init_utsname()->version, " "), | |
144 | init_utsname()->version, | |
145 | vendor, product, | |
146 | board ? "/" : "", | |
147 | board ? board : ""); | |
814e2c84 AI |
148 | } |
149 | ||
389d1fb1 JF |
150 | void flush_thread(void) |
151 | { | |
152 | struct task_struct *tsk = current; | |
153 | ||
24f1e32c | 154 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 | 155 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
1dcc8d7b | 156 | drop_fpu(tsk); |
389d1fb1 JF |
157 | } |
158 | ||
159 | static void hard_disable_TSC(void) | |
160 | { | |
161 | write_cr4(read_cr4() | X86_CR4_TSD); | |
162 | } | |
163 | ||
164 | void disable_TSC(void) | |
165 | { | |
166 | preempt_disable(); | |
167 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
168 | /* | |
169 | * Must flip the CPU state synchronously with | |
170 | * TIF_NOTSC in the current running context. | |
171 | */ | |
172 | hard_disable_TSC(); | |
173 | preempt_enable(); | |
174 | } | |
175 | ||
176 | static void hard_enable_TSC(void) | |
177 | { | |
178 | write_cr4(read_cr4() & ~X86_CR4_TSD); | |
179 | } | |
180 | ||
181 | static void enable_TSC(void) | |
182 | { | |
183 | preempt_disable(); | |
184 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
185 | /* | |
186 | * Must flip the CPU state synchronously with | |
187 | * TIF_NOTSC in the current running context. | |
188 | */ | |
189 | hard_enable_TSC(); | |
190 | preempt_enable(); | |
191 | } | |
192 | ||
193 | int get_tsc_mode(unsigned long adr) | |
194 | { | |
195 | unsigned int val; | |
196 | ||
197 | if (test_thread_flag(TIF_NOTSC)) | |
198 | val = PR_TSC_SIGSEGV; | |
199 | else | |
200 | val = PR_TSC_ENABLE; | |
201 | ||
202 | return put_user(val, (unsigned int __user *)adr); | |
203 | } | |
204 | ||
205 | int set_tsc_mode(unsigned int val) | |
206 | { | |
207 | if (val == PR_TSC_SIGSEGV) | |
208 | disable_TSC(); | |
209 | else if (val == PR_TSC_ENABLE) | |
210 | enable_TSC(); | |
211 | else | |
212 | return -EINVAL; | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
217 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
218 | struct tss_struct *tss) | |
219 | { | |
220 | struct thread_struct *prev, *next; | |
221 | ||
222 | prev = &prev_p->thread; | |
223 | next = &next_p->thread; | |
224 | ||
ea8e61b7 PZ |
225 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
226 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
227 | unsigned long debugctl = get_debugctlmsr(); | |
228 | ||
229 | debugctl &= ~DEBUGCTLMSR_BTF; | |
230 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
231 | debugctl |= DEBUGCTLMSR_BTF; | |
232 | ||
233 | update_debugctlmsr(debugctl); | |
234 | } | |
389d1fb1 | 235 | |
389d1fb1 JF |
236 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
237 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
238 | /* prev and next are different */ | |
239 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
240 | hard_disable_TSC(); | |
241 | else | |
242 | hard_enable_TSC(); | |
243 | } | |
244 | ||
245 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
246 | /* | |
247 | * Copy the relevant range of the IO bitmap. | |
248 | * Normally this is 128 bytes or less: | |
249 | */ | |
250 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
251 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
252 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
253 | /* | |
254 | * Clear any possible leftover bits: | |
255 | */ | |
256 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
257 | } | |
7c68af6e | 258 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
259 | } |
260 | ||
261 | int sys_fork(struct pt_regs *regs) | |
262 | { | |
263 | return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL); | |
264 | } | |
265 | ||
266 | /* | |
267 | * This is trivial, and on the face of it looks like it | |
268 | * could equally well be done in user mode. | |
269 | * | |
270 | * Not so, for quite unobvious reasons - register pressure. | |
271 | * In user mode vfork() cannot have a stack frame, and if | |
272 | * done by calling the "clone()" system call directly, you | |
273 | * do not have enough call-clobbered registers to hold all | |
274 | * the information you need. | |
275 | */ | |
276 | int sys_vfork(struct pt_regs *regs) | |
277 | { | |
278 | return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0, | |
279 | NULL, NULL); | |
280 | } | |
281 | ||
f839bbc5 BG |
282 | long |
283 | sys_clone(unsigned long clone_flags, unsigned long newsp, | |
284 | void __user *parent_tid, void __user *child_tid, struct pt_regs *regs) | |
285 | { | |
286 | if (!newsp) | |
287 | newsp = regs->sp; | |
288 | return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid); | |
289 | } | |
290 | ||
df59e7bf BG |
291 | /* |
292 | * This gets run with %si containing the | |
293 | * function to call, and %di containing | |
294 | * the "args". | |
295 | */ | |
296 | extern void kernel_thread_helper(void); | |
297 | ||
298 | /* | |
299 | * Create a kernel thread | |
300 | */ | |
301 | int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) | |
302 | { | |
303 | struct pt_regs regs; | |
304 | ||
305 | memset(®s, 0, sizeof(regs)); | |
306 | ||
307 | regs.si = (unsigned long) fn; | |
308 | regs.di = (unsigned long) arg; | |
309 | ||
310 | #ifdef CONFIG_X86_32 | |
311 | regs.ds = __USER_DS; | |
312 | regs.es = __USER_DS; | |
313 | regs.fs = __KERNEL_PERCPU; | |
314 | regs.gs = __KERNEL_STACK_CANARY; | |
864a0922 CG |
315 | #else |
316 | regs.ss = __KERNEL_DS; | |
df59e7bf BG |
317 | #endif |
318 | ||
319 | regs.orig_ax = -1; | |
320 | regs.ip = (unsigned long) kernel_thread_helper; | |
321 | regs.cs = __KERNEL_CS | get_kernel_rpl(); | |
1cf8343f | 322 | regs.flags = X86_EFLAGS_IF | X86_EFLAGS_BIT1; |
df59e7bf BG |
323 | |
324 | /* Ok, create the new process.. */ | |
325 | return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL); | |
326 | } | |
327 | EXPORT_SYMBOL(kernel_thread); | |
389d1fb1 | 328 | |
11cf88bd BG |
329 | /* |
330 | * sys_execve() executes a new program. | |
331 | */ | |
d7627467 DH |
332 | long sys_execve(const char __user *name, |
333 | const char __user *const __user *argv, | |
334 | const char __user *const __user *envp, struct pt_regs *regs) | |
11cf88bd BG |
335 | { |
336 | long error; | |
337 | char *filename; | |
338 | ||
339 | filename = getname(name); | |
340 | error = PTR_ERR(filename); | |
341 | if (IS_ERR(filename)) | |
342 | return error; | |
343 | error = do_execve(filename, argv, envp, regs); | |
344 | ||
345 | #ifdef CONFIG_X86_32 | |
346 | if (error == 0) { | |
347 | /* Make sure we don't return using sysenter.. */ | |
348 | set_thread_flag(TIF_IRET); | |
349 | } | |
350 | #endif | |
351 | ||
352 | putname(filename); | |
353 | return error; | |
354 | } | |
389d1fb1 | 355 | |
00dba564 TG |
356 | /* |
357 | * Idle related variables and functions | |
358 | */ | |
d1896049 | 359 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
360 | EXPORT_SYMBOL(boot_option_idle_override); |
361 | ||
362 | /* | |
363 | * Powermanagement idle function, if any.. | |
364 | */ | |
365 | void (*pm_idle)(void); | |
60b8b1de | 366 | #ifdef CONFIG_APM_MODULE |
00dba564 | 367 | EXPORT_SYMBOL(pm_idle); |
06ae40ce | 368 | #endif |
00dba564 | 369 | |
00dba564 TG |
370 | static inline int hlt_use_halt(void) |
371 | { | |
372 | return 1; | |
373 | } | |
00dba564 | 374 | |
90e24014 RW |
375 | #ifndef CONFIG_SMP |
376 | static inline void play_dead(void) | |
377 | { | |
378 | BUG(); | |
379 | } | |
380 | #endif | |
381 | ||
382 | #ifdef CONFIG_X86_64 | |
383 | void enter_idle(void) | |
384 | { | |
c6ae41e7 | 385 | this_cpu_write(is_idle, 1); |
90e24014 RW |
386 | atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); |
387 | } | |
388 | ||
389 | static void __exit_idle(void) | |
390 | { | |
391 | if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) | |
392 | return; | |
393 | atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); | |
394 | } | |
395 | ||
396 | /* Called from interrupts to signify idle end */ | |
397 | void exit_idle(void) | |
398 | { | |
399 | /* idle loop has pid 0 */ | |
400 | if (current->pid) | |
401 | return; | |
402 | __exit_idle(); | |
403 | } | |
404 | #endif | |
405 | ||
406 | /* | |
407 | * The idle thread. There's no useful work to be | |
408 | * done, so just try to conserve power and have a | |
409 | * low exit latency (ie sit in a loop waiting for | |
410 | * somebody to say that they'd like to reschedule) | |
411 | */ | |
412 | void cpu_idle(void) | |
413 | { | |
414 | /* | |
415 | * If we're the non-boot CPU, nothing set the stack canary up | |
416 | * for us. CPU0 already has it initialized but no harm in | |
417 | * doing it again. This is a good place for updating it, as | |
418 | * we wont ever return from this function (so the invalid | |
419 | * canaries already on the stack wont ever trigger). | |
420 | */ | |
421 | boot_init_stack_canary(); | |
422 | current_thread_info()->status |= TS_POLLING; | |
423 | ||
424 | while (1) { | |
425 | tick_nohz_idle_enter(); | |
426 | ||
427 | while (!need_resched()) { | |
428 | rmb(); | |
429 | ||
430 | if (cpu_is_offline(smp_processor_id())) | |
431 | play_dead(); | |
432 | ||
433 | /* | |
434 | * Idle routines should keep interrupts disabled | |
435 | * from here on, until they go to idle. | |
436 | * Otherwise, idle callbacks can misfire. | |
437 | */ | |
438 | local_touch_nmi(); | |
439 | local_irq_disable(); | |
440 | ||
441 | enter_idle(); | |
442 | ||
443 | /* Don't trace irqs off for idle */ | |
444 | stop_critical_timings(); | |
445 | ||
446 | /* enter_idle() needs rcu for notifiers */ | |
447 | rcu_idle_enter(); | |
448 | ||
449 | if (cpuidle_idle_call()) | |
450 | pm_idle(); | |
451 | ||
452 | rcu_idle_exit(); | |
453 | start_critical_timings(); | |
454 | ||
455 | /* In many cases the interrupt that ended idle | |
456 | has already called exit_idle. But some idle | |
457 | loops can be woken up without interrupt. */ | |
458 | __exit_idle(); | |
459 | } | |
460 | ||
461 | tick_nohz_idle_exit(); | |
462 | preempt_enable_no_resched(); | |
463 | schedule(); | |
464 | preempt_disable(); | |
465 | } | |
466 | } | |
467 | ||
00dba564 TG |
468 | /* |
469 | * We use this if we don't have any better | |
470 | * idle routine.. | |
471 | */ | |
472 | void default_idle(void) | |
473 | { | |
474 | if (hlt_use_halt()) { | |
48454650 SR |
475 | trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id()); |
476 | trace_cpu_idle_rcuidle(1, smp_processor_id()); | |
00dba564 TG |
477 | current_thread_info()->status &= ~TS_POLLING; |
478 | /* | |
479 | * TS_POLLING-cleared state must be visible before we | |
480 | * test NEED_RESCHED: | |
481 | */ | |
482 | smp_mb(); | |
483 | ||
484 | if (!need_resched()) | |
485 | safe_halt(); /* enables interrupts racelessly */ | |
486 | else | |
487 | local_irq_enable(); | |
488 | current_thread_info()->status |= TS_POLLING; | |
48454650 SR |
489 | trace_power_end_rcuidle(smp_processor_id()); |
490 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); | |
00dba564 TG |
491 | } else { |
492 | local_irq_enable(); | |
493 | /* loop is done by the caller */ | |
494 | cpu_relax(); | |
495 | } | |
496 | } | |
60b8b1de | 497 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
498 | EXPORT_SYMBOL(default_idle); |
499 | #endif | |
500 | ||
e5fd47bf KRW |
501 | bool set_pm_idle_to_default(void) |
502 | { | |
503 | bool ret = !!pm_idle; | |
504 | ||
505 | pm_idle = default_idle; | |
506 | ||
507 | return ret; | |
508 | } | |
d3ec5cae IV |
509 | void stop_this_cpu(void *dummy) |
510 | { | |
511 | local_irq_disable(); | |
512 | /* | |
513 | * Remove this CPU: | |
514 | */ | |
4f062896 | 515 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
516 | disable_local_APIC(); |
517 | ||
518 | for (;;) { | |
519 | if (hlt_works(smp_processor_id())) | |
520 | halt(); | |
521 | } | |
522 | } | |
523 | ||
7f424a8b PZ |
524 | /* Default MONITOR/MWAIT with no hints, used for default C1 state */ |
525 | static void mwait_idle(void) | |
526 | { | |
527 | if (!need_resched()) { | |
48454650 SR |
528 | trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id()); |
529 | trace_cpu_idle_rcuidle(1, smp_processor_id()); | |
349c004e | 530 | if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR)) |
e736ad54 PV |
531 | clflush((void *)¤t_thread_info()->flags); |
532 | ||
7f424a8b PZ |
533 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
534 | smp_mb(); | |
535 | if (!need_resched()) | |
536 | __sti_mwait(0, 0); | |
537 | else | |
538 | local_irq_enable(); | |
48454650 SR |
539 | trace_power_end_rcuidle(smp_processor_id()); |
540 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); | |
7f424a8b PZ |
541 | } else |
542 | local_irq_enable(); | |
543 | } | |
544 | ||
7f424a8b PZ |
545 | /* |
546 | * On SMP it's slightly faster (but much more power-consuming!) | |
547 | * to poll the ->work.need_resched flag instead of waiting for the | |
548 | * cross-CPU IPI to arrive. Use this option with caution. | |
549 | */ | |
550 | static void poll_idle(void) | |
551 | { | |
48454650 SR |
552 | trace_power_start_rcuidle(POWER_CSTATE, 0, smp_processor_id()); |
553 | trace_cpu_idle_rcuidle(0, smp_processor_id()); | |
7f424a8b | 554 | local_irq_enable(); |
2c7e9fd4 JK |
555 | while (!need_resched()) |
556 | cpu_relax(); | |
48454650 SR |
557 | trace_power_end_rcuidle(smp_processor_id()); |
558 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); | |
7f424a8b PZ |
559 | } |
560 | ||
e9623b35 TG |
561 | /* |
562 | * mwait selection logic: | |
563 | * | |
564 | * It depends on the CPU. For AMD CPUs that support MWAIT this is | |
565 | * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings | |
566 | * then depend on a clock divisor and current Pstate of the core. If | |
567 | * all cores of a processor are in halt state (C1) the processor can | |
568 | * enter the C1E (C1 enhanced) state. If mwait is used this will never | |
569 | * happen. | |
570 | * | |
571 | * idle=mwait overrides this decision and forces the usage of mwait. | |
572 | */ | |
09fd4b4e TG |
573 | |
574 | #define MWAIT_INFO 0x05 | |
575 | #define MWAIT_ECX_EXTENDED_INFO 0x01 | |
576 | #define MWAIT_EDX_C1 0xf0 | |
577 | ||
1c9d16e3 | 578 | int mwait_usable(const struct cpuinfo_x86 *c) |
e9623b35 | 579 | { |
09fd4b4e TG |
580 | u32 eax, ebx, ecx, edx; |
581 | ||
19209bbb | 582 | /* Use mwait if idle=mwait boot option is given */ |
d1896049 | 583 | if (boot_option_idle_override == IDLE_FORCE_MWAIT) |
e9623b35 TG |
584 | return 1; |
585 | ||
19209bbb SB |
586 | /* |
587 | * Any idle= boot option other than idle=mwait means that we must not | |
588 | * use mwait. Eg: idle=halt or idle=poll or idle=nomwait | |
589 | */ | |
590 | if (boot_option_idle_override != IDLE_NO_OVERRIDE) | |
591 | return 0; | |
592 | ||
09fd4b4e TG |
593 | if (c->cpuid_level < MWAIT_INFO) |
594 | return 0; | |
595 | ||
596 | cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx); | |
597 | /* Check, whether EDX has extended info about MWAIT */ | |
598 | if (!(ecx & MWAIT_ECX_EXTENDED_INFO)) | |
599 | return 1; | |
600 | ||
601 | /* | |
602 | * edx enumeratios MONITOR/MWAIT extensions. Check, whether | |
603 | * C1 supports MWAIT | |
604 | */ | |
605 | return (edx & MWAIT_EDX_C1); | |
e9623b35 TG |
606 | } |
607 | ||
02c68a02 LB |
608 | bool amd_e400_c1e_detected; |
609 | EXPORT_SYMBOL(amd_e400_c1e_detected); | |
aa276e1c | 610 | |
02c68a02 | 611 | static cpumask_var_t amd_e400_c1e_mask; |
4faac97d | 612 | |
02c68a02 | 613 | void amd_e400_remove_cpu(int cpu) |
4faac97d | 614 | { |
02c68a02 LB |
615 | if (amd_e400_c1e_mask != NULL) |
616 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); | |
4faac97d TG |
617 | } |
618 | ||
aa276e1c | 619 | /* |
02c68a02 | 620 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
aa276e1c TG |
621 | * pending message MSR. If we detect C1E, then we handle it the same |
622 | * way as C3 power states (local apic timer and TSC stop) | |
623 | */ | |
02c68a02 | 624 | static void amd_e400_idle(void) |
aa276e1c | 625 | { |
aa276e1c TG |
626 | if (need_resched()) |
627 | return; | |
628 | ||
02c68a02 | 629 | if (!amd_e400_c1e_detected) { |
aa276e1c TG |
630 | u32 lo, hi; |
631 | ||
632 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
e8c534ec | 633 | |
aa276e1c | 634 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
02c68a02 | 635 | amd_e400_c1e_detected = true; |
40fb1715 | 636 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 | 637 | mark_tsc_unstable("TSC halt in AMD C1E"); |
c767a54b | 638 | pr_info("System has AMD C1E enabled\n"); |
aa276e1c TG |
639 | } |
640 | } | |
641 | ||
02c68a02 | 642 | if (amd_e400_c1e_detected) { |
aa276e1c TG |
643 | int cpu = smp_processor_id(); |
644 | ||
02c68a02 LB |
645 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
646 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); | |
0beefa20 | 647 | /* |
f833bab8 | 648 | * Force broadcast so ACPI can not interfere. |
0beefa20 | 649 | */ |
aa276e1c TG |
650 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
651 | &cpu); | |
c767a54b | 652 | pr_info("Switch to broadcast mode on CPU%d\n", cpu); |
aa276e1c TG |
653 | } |
654 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
0beefa20 | 655 | |
aa276e1c | 656 | default_idle(); |
0beefa20 TG |
657 | |
658 | /* | |
659 | * The switch back from broadcast mode needs to be | |
660 | * called with interrupts disabled. | |
661 | */ | |
662 | local_irq_disable(); | |
663 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
664 | local_irq_enable(); | |
aa276e1c TG |
665 | } else |
666 | default_idle(); | |
667 | } | |
668 | ||
7f424a8b PZ |
669 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) |
670 | { | |
3e5095d1 | 671 | #ifdef CONFIG_SMP |
7f424a8b | 672 | if (pm_idle == poll_idle && smp_num_siblings > 1) { |
c767a54b | 673 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
7f424a8b PZ |
674 | } |
675 | #endif | |
6ddd2a27 TG |
676 | if (pm_idle) |
677 | return; | |
678 | ||
e9623b35 | 679 | if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { |
7f424a8b | 680 | /* |
7f424a8b PZ |
681 | * One CPU supports mwait => All CPUs supports mwait |
682 | */ | |
c767a54b | 683 | pr_info("using mwait in idle threads\n"); |
6ddd2a27 | 684 | pm_idle = mwait_idle; |
9d8888c2 HR |
685 | } else if (cpu_has_amd_erratum(amd_erratum_400)) { |
686 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ | |
c767a54b | 687 | pr_info("using AMD E400 aware idle routine\n"); |
02c68a02 | 688 | pm_idle = amd_e400_idle; |
6ddd2a27 TG |
689 | } else |
690 | pm_idle = default_idle; | |
7f424a8b PZ |
691 | } |
692 | ||
02c68a02 | 693 | void __init init_amd_e400_c1e_mask(void) |
30e1e6d1 | 694 | { |
02c68a02 LB |
695 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
696 | if (pm_idle == amd_e400_idle) | |
697 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); | |
30e1e6d1 RR |
698 | } |
699 | ||
7f424a8b PZ |
700 | static int __init idle_setup(char *str) |
701 | { | |
ab6bc3e3 CG |
702 | if (!str) |
703 | return -EINVAL; | |
704 | ||
7f424a8b | 705 | if (!strcmp(str, "poll")) { |
c767a54b | 706 | pr_info("using polling idle threads\n"); |
7f424a8b | 707 | pm_idle = poll_idle; |
d1896049 TR |
708 | boot_option_idle_override = IDLE_POLL; |
709 | } else if (!strcmp(str, "mwait")) { | |
710 | boot_option_idle_override = IDLE_FORCE_MWAIT; | |
af0d6a0a | 711 | WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n"); |
d1896049 | 712 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
713 | /* |
714 | * When the boot option of idle=halt is added, halt is | |
715 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
716 | * won't be used again. | |
717 | * To continue to load the CPU idle driver, don't touch | |
718 | * the boot_option_idle_override. | |
719 | */ | |
720 | pm_idle = default_idle; | |
d1896049 | 721 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
722 | } else if (!strcmp(str, "nomwait")) { |
723 | /* | |
724 | * If the boot option of "idle=nomwait" is added, | |
725 | * it means that mwait will be disabled for CPU C2/C3 | |
726 | * states. In such case it won't touch the variable | |
727 | * of boot_option_idle_override. | |
728 | */ | |
d1896049 | 729 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 730 | } else |
7f424a8b PZ |
731 | return -1; |
732 | ||
7f424a8b PZ |
733 | return 0; |
734 | } | |
735 | early_param("idle", idle_setup); | |
736 | ||
9d62dcdf AW |
737 | unsigned long arch_align_stack(unsigned long sp) |
738 | { | |
739 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
740 | sp -= get_random_int() % 8192; | |
741 | return sp & ~0xf; | |
742 | } | |
743 | ||
744 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
745 | { | |
746 | unsigned long range_end = mm->brk + 0x02000000; | |
747 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
748 | } | |
749 |