Commit | Line | Data |
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61c4628b SS |
1 | #include <linux/errno.h> |
2 | #include <linux/kernel.h> | |
3 | #include <linux/mm.h> | |
4 | #include <linux/smp.h> | |
389d1fb1 | 5 | #include <linux/prctl.h> |
61c4628b SS |
6 | #include <linux/slab.h> |
7 | #include <linux/sched.h> | |
7f424a8b PZ |
8 | #include <linux/module.h> |
9 | #include <linux/pm.h> | |
aa276e1c | 10 | #include <linux/clockchips.h> |
9d62dcdf | 11 | #include <linux/random.h> |
7c68af6e | 12 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
13 | #include <linux/dmi.h> |
14 | #include <linux/utsname.h> | |
61613521 | 15 | #include <trace/events/power.h> |
24f1e32c | 16 | #include <linux/hw_breakpoint.h> |
93789b32 | 17 | #include <asm/cpu.h> |
c1e3b377 | 18 | #include <asm/system.h> |
d3ec5cae | 19 | #include <asm/apic.h> |
2c1b284e | 20 | #include <asm/syscalls.h> |
389d1fb1 JF |
21 | #include <asm/idle.h> |
22 | #include <asm/uaccess.h> | |
23 | #include <asm/i387.h> | |
66cb5917 | 24 | #include <asm/debugreg.h> |
c1e3b377 | 25 | |
aa283f49 | 26 | struct kmem_cache *task_xstate_cachep; |
5ee481da | 27 | EXPORT_SYMBOL_GPL(task_xstate_cachep); |
61c4628b SS |
28 | |
29 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) | |
30 | { | |
86603283 AK |
31 | int ret; |
32 | ||
61c4628b | 33 | *dst = *src; |
86603283 AK |
34 | if (fpu_allocated(&src->thread.fpu)) { |
35 | memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu)); | |
36 | ret = fpu_alloc(&dst->thread.fpu); | |
37 | if (ret) | |
38 | return ret; | |
39 | fpu_copy(&dst->thread.fpu, &src->thread.fpu); | |
aa283f49 | 40 | } |
61c4628b SS |
41 | return 0; |
42 | } | |
43 | ||
aa283f49 | 44 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 45 | { |
86603283 | 46 | fpu_free(&tsk->thread.fpu); |
aa283f49 SS |
47 | } |
48 | ||
aa283f49 SS |
49 | void free_thread_info(struct thread_info *ti) |
50 | { | |
51 | free_thread_xstate(ti->task); | |
1679f271 | 52 | free_pages((unsigned long)ti, get_order(THREAD_SIZE)); |
61c4628b SS |
53 | } |
54 | ||
55 | void arch_task_cache_init(void) | |
56 | { | |
57 | task_xstate_cachep = | |
58 | kmem_cache_create("task_xstate", xstate_size, | |
59 | __alignof__(union thread_xstate), | |
2dff4405 | 60 | SLAB_PANIC | SLAB_NOTRACK, NULL); |
61c4628b | 61 | } |
7f424a8b | 62 | |
389d1fb1 JF |
63 | /* |
64 | * Free current thread data structures etc.. | |
65 | */ | |
66 | void exit_thread(void) | |
67 | { | |
68 | struct task_struct *me = current; | |
69 | struct thread_struct *t = &me->thread; | |
250981e6 | 70 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 71 | |
250981e6 | 72 | if (bp) { |
389d1fb1 JF |
73 | struct tss_struct *tss = &per_cpu(init_tss, get_cpu()); |
74 | ||
389d1fb1 JF |
75 | t->io_bitmap_ptr = NULL; |
76 | clear_thread_flag(TIF_IO_BITMAP); | |
77 | /* | |
78 | * Careful, clear this in the TSS too: | |
79 | */ | |
80 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
81 | t->io_bitmap_max = 0; | |
82 | put_cpu(); | |
250981e6 | 83 | kfree(bp); |
389d1fb1 | 84 | } |
389d1fb1 JF |
85 | } |
86 | ||
3bef4447 BG |
87 | void show_regs(struct pt_regs *regs) |
88 | { | |
89 | show_registers(regs); | |
e8e999cf | 90 | show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs), 0); |
3bef4447 BG |
91 | } |
92 | ||
814e2c84 AI |
93 | void show_regs_common(void) |
94 | { | |
84e383b3 | 95 | const char *vendor, *product, *board; |
814e2c84 | 96 | |
84e383b3 NC |
97 | vendor = dmi_get_system_info(DMI_SYS_VENDOR); |
98 | if (!vendor) | |
99 | vendor = ""; | |
a1884b8e AI |
100 | product = dmi_get_system_info(DMI_PRODUCT_NAME); |
101 | if (!product) | |
102 | product = ""; | |
814e2c84 | 103 | |
84e383b3 NC |
104 | /* Board Name is optional */ |
105 | board = dmi_get_system_info(DMI_BOARD_NAME); | |
106 | ||
d015a092 | 107 | printk(KERN_CONT "\n"); |
84e383b3 | 108 | printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s", |
814e2c84 AI |
109 | current->pid, current->comm, print_tainted(), |
110 | init_utsname()->release, | |
111 | (int)strcspn(init_utsname()->version, " "), | |
84e383b3 | 112 | init_utsname()->version); |
fd8fa4d3 JB |
113 | printk(KERN_CONT " %s %s", vendor, product); |
114 | if (board) | |
115 | printk(KERN_CONT "/%s", board); | |
84e383b3 | 116 | printk(KERN_CONT "\n"); |
814e2c84 AI |
117 | } |
118 | ||
389d1fb1 JF |
119 | void flush_thread(void) |
120 | { | |
121 | struct task_struct *tsk = current; | |
122 | ||
24f1e32c | 123 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 JF |
124 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
125 | /* | |
126 | * Forget coprocessor state.. | |
127 | */ | |
128 | tsk->fpu_counter = 0; | |
129 | clear_fpu(tsk); | |
130 | clear_used_math(); | |
131 | } | |
132 | ||
133 | static void hard_disable_TSC(void) | |
134 | { | |
135 | write_cr4(read_cr4() | X86_CR4_TSD); | |
136 | } | |
137 | ||
138 | void disable_TSC(void) | |
139 | { | |
140 | preempt_disable(); | |
141 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
142 | /* | |
143 | * Must flip the CPU state synchronously with | |
144 | * TIF_NOTSC in the current running context. | |
145 | */ | |
146 | hard_disable_TSC(); | |
147 | preempt_enable(); | |
148 | } | |
149 | ||
150 | static void hard_enable_TSC(void) | |
151 | { | |
152 | write_cr4(read_cr4() & ~X86_CR4_TSD); | |
153 | } | |
154 | ||
155 | static void enable_TSC(void) | |
156 | { | |
157 | preempt_disable(); | |
158 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
159 | /* | |
160 | * Must flip the CPU state synchronously with | |
161 | * TIF_NOTSC in the current running context. | |
162 | */ | |
163 | hard_enable_TSC(); | |
164 | preempt_enable(); | |
165 | } | |
166 | ||
167 | int get_tsc_mode(unsigned long adr) | |
168 | { | |
169 | unsigned int val; | |
170 | ||
171 | if (test_thread_flag(TIF_NOTSC)) | |
172 | val = PR_TSC_SIGSEGV; | |
173 | else | |
174 | val = PR_TSC_ENABLE; | |
175 | ||
176 | return put_user(val, (unsigned int __user *)adr); | |
177 | } | |
178 | ||
179 | int set_tsc_mode(unsigned int val) | |
180 | { | |
181 | if (val == PR_TSC_SIGSEGV) | |
182 | disable_TSC(); | |
183 | else if (val == PR_TSC_ENABLE) | |
184 | enable_TSC(); | |
185 | else | |
186 | return -EINVAL; | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
192 | struct tss_struct *tss) | |
193 | { | |
194 | struct thread_struct *prev, *next; | |
195 | ||
196 | prev = &prev_p->thread; | |
197 | next = &next_p->thread; | |
198 | ||
ea8e61b7 PZ |
199 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
200 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
201 | unsigned long debugctl = get_debugctlmsr(); | |
202 | ||
203 | debugctl &= ~DEBUGCTLMSR_BTF; | |
204 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
205 | debugctl |= DEBUGCTLMSR_BTF; | |
206 | ||
207 | update_debugctlmsr(debugctl); | |
208 | } | |
389d1fb1 | 209 | |
389d1fb1 JF |
210 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
211 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
212 | /* prev and next are different */ | |
213 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
214 | hard_disable_TSC(); | |
215 | else | |
216 | hard_enable_TSC(); | |
217 | } | |
218 | ||
219 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
220 | /* | |
221 | * Copy the relevant range of the IO bitmap. | |
222 | * Normally this is 128 bytes or less: | |
223 | */ | |
224 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
225 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
226 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
227 | /* | |
228 | * Clear any possible leftover bits: | |
229 | */ | |
230 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
231 | } | |
7c68af6e | 232 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
233 | } |
234 | ||
235 | int sys_fork(struct pt_regs *regs) | |
236 | { | |
237 | return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL); | |
238 | } | |
239 | ||
240 | /* | |
241 | * This is trivial, and on the face of it looks like it | |
242 | * could equally well be done in user mode. | |
243 | * | |
244 | * Not so, for quite unobvious reasons - register pressure. | |
245 | * In user mode vfork() cannot have a stack frame, and if | |
246 | * done by calling the "clone()" system call directly, you | |
247 | * do not have enough call-clobbered registers to hold all | |
248 | * the information you need. | |
249 | */ | |
250 | int sys_vfork(struct pt_regs *regs) | |
251 | { | |
252 | return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0, | |
253 | NULL, NULL); | |
254 | } | |
255 | ||
f839bbc5 BG |
256 | long |
257 | sys_clone(unsigned long clone_flags, unsigned long newsp, | |
258 | void __user *parent_tid, void __user *child_tid, struct pt_regs *regs) | |
259 | { | |
260 | if (!newsp) | |
261 | newsp = regs->sp; | |
262 | return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid); | |
263 | } | |
264 | ||
df59e7bf BG |
265 | /* |
266 | * This gets run with %si containing the | |
267 | * function to call, and %di containing | |
268 | * the "args". | |
269 | */ | |
270 | extern void kernel_thread_helper(void); | |
271 | ||
272 | /* | |
273 | * Create a kernel thread | |
274 | */ | |
275 | int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) | |
276 | { | |
277 | struct pt_regs regs; | |
278 | ||
279 | memset(®s, 0, sizeof(regs)); | |
280 | ||
281 | regs.si = (unsigned long) fn; | |
282 | regs.di = (unsigned long) arg; | |
283 | ||
284 | #ifdef CONFIG_X86_32 | |
285 | regs.ds = __USER_DS; | |
286 | regs.es = __USER_DS; | |
287 | regs.fs = __KERNEL_PERCPU; | |
288 | regs.gs = __KERNEL_STACK_CANARY; | |
864a0922 CG |
289 | #else |
290 | regs.ss = __KERNEL_DS; | |
df59e7bf BG |
291 | #endif |
292 | ||
293 | regs.orig_ax = -1; | |
294 | regs.ip = (unsigned long) kernel_thread_helper; | |
295 | regs.cs = __KERNEL_CS | get_kernel_rpl(); | |
296 | regs.flags = X86_EFLAGS_IF | 0x2; | |
297 | ||
298 | /* Ok, create the new process.. */ | |
299 | return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL); | |
300 | } | |
301 | EXPORT_SYMBOL(kernel_thread); | |
389d1fb1 | 302 | |
11cf88bd BG |
303 | /* |
304 | * sys_execve() executes a new program. | |
305 | */ | |
d7627467 DH |
306 | long sys_execve(const char __user *name, |
307 | const char __user *const __user *argv, | |
308 | const char __user *const __user *envp, struct pt_regs *regs) | |
11cf88bd BG |
309 | { |
310 | long error; | |
311 | char *filename; | |
312 | ||
313 | filename = getname(name); | |
314 | error = PTR_ERR(filename); | |
315 | if (IS_ERR(filename)) | |
316 | return error; | |
317 | error = do_execve(filename, argv, envp, regs); | |
318 | ||
319 | #ifdef CONFIG_X86_32 | |
320 | if (error == 0) { | |
321 | /* Make sure we don't return using sysenter.. */ | |
322 | set_thread_flag(TIF_IRET); | |
323 | } | |
324 | #endif | |
325 | ||
326 | putname(filename); | |
327 | return error; | |
328 | } | |
389d1fb1 | 329 | |
00dba564 TG |
330 | /* |
331 | * Idle related variables and functions | |
332 | */ | |
d1896049 | 333 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
334 | EXPORT_SYMBOL(boot_option_idle_override); |
335 | ||
336 | /* | |
337 | * Powermanagement idle function, if any.. | |
338 | */ | |
339 | void (*pm_idle)(void); | |
06ae40ce | 340 | #if defined(CONFIG_APM_MODULE) && defined(CONFIG_APM_CPU_IDLE) |
00dba564 | 341 | EXPORT_SYMBOL(pm_idle); |
06ae40ce | 342 | #endif |
00dba564 TG |
343 | |
344 | #ifdef CONFIG_X86_32 | |
345 | /* | |
346 | * This halt magic was a workaround for ancient floppy DMA | |
347 | * wreckage. It should be safe to remove. | |
348 | */ | |
349 | static int hlt_counter; | |
350 | void disable_hlt(void) | |
351 | { | |
352 | hlt_counter++; | |
353 | } | |
354 | EXPORT_SYMBOL(disable_hlt); | |
355 | ||
356 | void enable_hlt(void) | |
357 | { | |
358 | hlt_counter--; | |
359 | } | |
360 | EXPORT_SYMBOL(enable_hlt); | |
361 | ||
362 | static inline int hlt_use_halt(void) | |
363 | { | |
364 | return (!hlt_counter && boot_cpu_data.hlt_works_ok); | |
365 | } | |
366 | #else | |
367 | static inline int hlt_use_halt(void) | |
368 | { | |
369 | return 1; | |
370 | } | |
371 | #endif | |
372 | ||
373 | /* | |
374 | * We use this if we don't have any better | |
375 | * idle routine.. | |
376 | */ | |
377 | void default_idle(void) | |
378 | { | |
379 | if (hlt_use_halt()) { | |
6f4f2723 | 380 | trace_power_start(POWER_CSTATE, 1, smp_processor_id()); |
25e41933 | 381 | trace_cpu_idle(1, smp_processor_id()); |
00dba564 TG |
382 | current_thread_info()->status &= ~TS_POLLING; |
383 | /* | |
384 | * TS_POLLING-cleared state must be visible before we | |
385 | * test NEED_RESCHED: | |
386 | */ | |
387 | smp_mb(); | |
388 | ||
389 | if (!need_resched()) | |
390 | safe_halt(); /* enables interrupts racelessly */ | |
391 | else | |
392 | local_irq_enable(); | |
393 | current_thread_info()->status |= TS_POLLING; | |
f77cfe4e TR |
394 | trace_power_end(smp_processor_id()); |
395 | trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); | |
00dba564 TG |
396 | } else { |
397 | local_irq_enable(); | |
398 | /* loop is done by the caller */ | |
399 | cpu_relax(); | |
400 | } | |
401 | } | |
06ae40ce | 402 | #if defined(CONFIG_APM_MODULE) && defined(CONFIG_APM_CPU_IDLE) |
00dba564 TG |
403 | EXPORT_SYMBOL(default_idle); |
404 | #endif | |
405 | ||
d3ec5cae IV |
406 | void stop_this_cpu(void *dummy) |
407 | { | |
408 | local_irq_disable(); | |
409 | /* | |
410 | * Remove this CPU: | |
411 | */ | |
4f062896 | 412 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
413 | disable_local_APIC(); |
414 | ||
415 | for (;;) { | |
416 | if (hlt_works(smp_processor_id())) | |
417 | halt(); | |
418 | } | |
419 | } | |
420 | ||
7f424a8b PZ |
421 | static void do_nothing(void *unused) |
422 | { | |
423 | } | |
424 | ||
425 | /* | |
426 | * cpu_idle_wait - Used to ensure that all the CPUs discard old value of | |
427 | * pm_idle and update to new pm_idle value. Required while changing pm_idle | |
428 | * handler on SMP systems. | |
429 | * | |
430 | * Caller must have changed pm_idle to the new value before the call. Old | |
431 | * pm_idle value will not be used by any CPU after the return of this function. | |
432 | */ | |
433 | void cpu_idle_wait(void) | |
434 | { | |
435 | smp_mb(); | |
436 | /* kick all the CPUs so that they exit out of pm_idle */ | |
127a237a | 437 | smp_call_function(do_nothing, NULL, 1); |
7f424a8b PZ |
438 | } |
439 | EXPORT_SYMBOL_GPL(cpu_idle_wait); | |
440 | ||
441 | /* | |
442 | * This uses new MONITOR/MWAIT instructions on P4 processors with PNI, | |
443 | * which can obviate IPI to trigger checking of need_resched. | |
444 | * We execute MONITOR against need_resched and enter optimized wait state | |
445 | * through MWAIT. Whenever someone changes need_resched, we would be woken | |
446 | * up from MWAIT (without an IPI). | |
447 | * | |
448 | * New with Core Duo processors, MWAIT can take some hints based on CPU | |
449 | * capability. | |
450 | */ | |
451 | void mwait_idle_with_hints(unsigned long ax, unsigned long cx) | |
452 | { | |
453 | if (!need_resched()) { | |
349c004e | 454 | if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR)) |
e736ad54 PV |
455 | clflush((void *)¤t_thread_info()->flags); |
456 | ||
7f424a8b PZ |
457 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
458 | smp_mb(); | |
459 | if (!need_resched()) | |
460 | __mwait(ax, cx); | |
461 | } | |
462 | } | |
463 | ||
464 | /* Default MONITOR/MWAIT with no hints, used for default C1 state */ | |
465 | static void mwait_idle(void) | |
466 | { | |
467 | if (!need_resched()) { | |
6f4f2723 | 468 | trace_power_start(POWER_CSTATE, 1, smp_processor_id()); |
25e41933 | 469 | trace_cpu_idle(1, smp_processor_id()); |
349c004e | 470 | if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR)) |
e736ad54 PV |
471 | clflush((void *)¤t_thread_info()->flags); |
472 | ||
7f424a8b PZ |
473 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
474 | smp_mb(); | |
475 | if (!need_resched()) | |
476 | __sti_mwait(0, 0); | |
477 | else | |
478 | local_irq_enable(); | |
f77cfe4e TR |
479 | trace_power_end(smp_processor_id()); |
480 | trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); | |
7f424a8b PZ |
481 | } else |
482 | local_irq_enable(); | |
483 | } | |
484 | ||
7f424a8b PZ |
485 | /* |
486 | * On SMP it's slightly faster (but much more power-consuming!) | |
487 | * to poll the ->work.need_resched flag instead of waiting for the | |
488 | * cross-CPU IPI to arrive. Use this option with caution. | |
489 | */ | |
490 | static void poll_idle(void) | |
491 | { | |
6f4f2723 | 492 | trace_power_start(POWER_CSTATE, 0, smp_processor_id()); |
25e41933 | 493 | trace_cpu_idle(0, smp_processor_id()); |
7f424a8b | 494 | local_irq_enable(); |
2c7e9fd4 JK |
495 | while (!need_resched()) |
496 | cpu_relax(); | |
25e41933 TR |
497 | trace_power_end(smp_processor_id()); |
498 | trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); | |
7f424a8b PZ |
499 | } |
500 | ||
e9623b35 TG |
501 | /* |
502 | * mwait selection logic: | |
503 | * | |
504 | * It depends on the CPU. For AMD CPUs that support MWAIT this is | |
505 | * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings | |
506 | * then depend on a clock divisor and current Pstate of the core. If | |
507 | * all cores of a processor are in halt state (C1) the processor can | |
508 | * enter the C1E (C1 enhanced) state. If mwait is used this will never | |
509 | * happen. | |
510 | * | |
511 | * idle=mwait overrides this decision and forces the usage of mwait. | |
512 | */ | |
09fd4b4e TG |
513 | |
514 | #define MWAIT_INFO 0x05 | |
515 | #define MWAIT_ECX_EXTENDED_INFO 0x01 | |
516 | #define MWAIT_EDX_C1 0xf0 | |
517 | ||
1c9d16e3 | 518 | int mwait_usable(const struct cpuinfo_x86 *c) |
e9623b35 | 519 | { |
09fd4b4e TG |
520 | u32 eax, ebx, ecx, edx; |
521 | ||
d1896049 | 522 | if (boot_option_idle_override == IDLE_FORCE_MWAIT) |
e9623b35 TG |
523 | return 1; |
524 | ||
09fd4b4e TG |
525 | if (c->cpuid_level < MWAIT_INFO) |
526 | return 0; | |
527 | ||
528 | cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx); | |
529 | /* Check, whether EDX has extended info about MWAIT */ | |
530 | if (!(ecx & MWAIT_ECX_EXTENDED_INFO)) | |
531 | return 1; | |
532 | ||
533 | /* | |
534 | * edx enumeratios MONITOR/MWAIT extensions. Check, whether | |
535 | * C1 supports MWAIT | |
536 | */ | |
537 | return (edx & MWAIT_EDX_C1); | |
e9623b35 TG |
538 | } |
539 | ||
02c68a02 LB |
540 | bool amd_e400_c1e_detected; |
541 | EXPORT_SYMBOL(amd_e400_c1e_detected); | |
aa276e1c | 542 | |
02c68a02 | 543 | static cpumask_var_t amd_e400_c1e_mask; |
4faac97d | 544 | |
02c68a02 | 545 | void amd_e400_remove_cpu(int cpu) |
4faac97d | 546 | { |
02c68a02 LB |
547 | if (amd_e400_c1e_mask != NULL) |
548 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); | |
4faac97d TG |
549 | } |
550 | ||
aa276e1c | 551 | /* |
02c68a02 | 552 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
aa276e1c TG |
553 | * pending message MSR. If we detect C1E, then we handle it the same |
554 | * way as C3 power states (local apic timer and TSC stop) | |
555 | */ | |
02c68a02 | 556 | static void amd_e400_idle(void) |
aa276e1c | 557 | { |
aa276e1c TG |
558 | if (need_resched()) |
559 | return; | |
560 | ||
02c68a02 | 561 | if (!amd_e400_c1e_detected) { |
aa276e1c TG |
562 | u32 lo, hi; |
563 | ||
564 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
e8c534ec | 565 | |
aa276e1c | 566 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
02c68a02 | 567 | amd_e400_c1e_detected = true; |
40fb1715 | 568 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 AH |
569 | mark_tsc_unstable("TSC halt in AMD C1E"); |
570 | printk(KERN_INFO "System has AMD C1E enabled\n"); | |
aa276e1c TG |
571 | } |
572 | } | |
573 | ||
02c68a02 | 574 | if (amd_e400_c1e_detected) { |
aa276e1c TG |
575 | int cpu = smp_processor_id(); |
576 | ||
02c68a02 LB |
577 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
578 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); | |
0beefa20 | 579 | /* |
f833bab8 | 580 | * Force broadcast so ACPI can not interfere. |
0beefa20 | 581 | */ |
aa276e1c TG |
582 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
583 | &cpu); | |
584 | printk(KERN_INFO "Switch to broadcast mode on CPU%d\n", | |
585 | cpu); | |
586 | } | |
587 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
0beefa20 | 588 | |
aa276e1c | 589 | default_idle(); |
0beefa20 TG |
590 | |
591 | /* | |
592 | * The switch back from broadcast mode needs to be | |
593 | * called with interrupts disabled. | |
594 | */ | |
595 | local_irq_disable(); | |
596 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
597 | local_irq_enable(); | |
aa276e1c TG |
598 | } else |
599 | default_idle(); | |
600 | } | |
601 | ||
7f424a8b PZ |
602 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) |
603 | { | |
3e5095d1 | 604 | #ifdef CONFIG_SMP |
7f424a8b | 605 | if (pm_idle == poll_idle && smp_num_siblings > 1) { |
d6dd6921 | 606 | printk_once(KERN_WARNING "WARNING: polling idle and HT enabled," |
7f424a8b PZ |
607 | " performance may degrade.\n"); |
608 | } | |
609 | #endif | |
6ddd2a27 TG |
610 | if (pm_idle) |
611 | return; | |
612 | ||
e9623b35 | 613 | if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { |
7f424a8b | 614 | /* |
7f424a8b PZ |
615 | * One CPU supports mwait => All CPUs supports mwait |
616 | */ | |
6ddd2a27 TG |
617 | printk(KERN_INFO "using mwait in idle threads.\n"); |
618 | pm_idle = mwait_idle; | |
9d8888c2 HR |
619 | } else if (cpu_has_amd_erratum(amd_erratum_400)) { |
620 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ | |
02c68a02 LB |
621 | printk(KERN_INFO "using AMD E400 aware idle routine\n"); |
622 | pm_idle = amd_e400_idle; | |
6ddd2a27 TG |
623 | } else |
624 | pm_idle = default_idle; | |
7f424a8b PZ |
625 | } |
626 | ||
02c68a02 | 627 | void __init init_amd_e400_c1e_mask(void) |
30e1e6d1 | 628 | { |
02c68a02 LB |
629 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
630 | if (pm_idle == amd_e400_idle) | |
631 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); | |
30e1e6d1 RR |
632 | } |
633 | ||
7f424a8b PZ |
634 | static int __init idle_setup(char *str) |
635 | { | |
ab6bc3e3 CG |
636 | if (!str) |
637 | return -EINVAL; | |
638 | ||
7f424a8b PZ |
639 | if (!strcmp(str, "poll")) { |
640 | printk("using polling idle threads.\n"); | |
641 | pm_idle = poll_idle; | |
d1896049 TR |
642 | boot_option_idle_override = IDLE_POLL; |
643 | } else if (!strcmp(str, "mwait")) { | |
644 | boot_option_idle_override = IDLE_FORCE_MWAIT; | |
af0d6a0a | 645 | WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n"); |
d1896049 | 646 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
647 | /* |
648 | * When the boot option of idle=halt is added, halt is | |
649 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
650 | * won't be used again. | |
651 | * To continue to load the CPU idle driver, don't touch | |
652 | * the boot_option_idle_override. | |
653 | */ | |
654 | pm_idle = default_idle; | |
d1896049 | 655 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
656 | } else if (!strcmp(str, "nomwait")) { |
657 | /* | |
658 | * If the boot option of "idle=nomwait" is added, | |
659 | * it means that mwait will be disabled for CPU C2/C3 | |
660 | * states. In such case it won't touch the variable | |
661 | * of boot_option_idle_override. | |
662 | */ | |
d1896049 | 663 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 664 | } else |
7f424a8b PZ |
665 | return -1; |
666 | ||
7f424a8b PZ |
667 | return 0; |
668 | } | |
669 | early_param("idle", idle_setup); | |
670 | ||
9d62dcdf AW |
671 | unsigned long arch_align_stack(unsigned long sp) |
672 | { | |
673 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
674 | sp -= get_random_int() % 8192; | |
675 | return sp & ~0xf; | |
676 | } | |
677 | ||
678 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
679 | { | |
680 | unsigned long range_end = mm->brk + 0x02000000; | |
681 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
682 | } | |
683 |