[linux-2.6-block.git] / arch / x86 / kernel / process.c

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/prctl.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/clockchips.h>
#include <linux/random.h>
#include <linux/user-return-notifier.h>
#include <linux/dmi.h>
#include <linux/utsname.h>
#include <linux/stackprotector.h>
#include <linux/tick.h>
#include <linux/cpuidle.h>
#include <trace/events/power.h>
#include <linux/hw_breakpoint.h>
#include <asm/cpu.h>
#include <asm/apic.h>
#include <asm/syscalls.h>
#include <asm/idle.h>
#include <asm/uaccess.h>
#include <asm/i387.h>
#include <asm/fpu-internal.h>
#include <asm/debugreg.h>
#include <asm/nmi.h>
#include <asm/tlbflush.h>

/*
 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
 * no more per-task TSS's. The TSS size is kept cacheline-aligned
 * so they are allowed to end up in the .data..cacheline_aligned
 * section. Since TSS's are completely CPU-local, we want them
 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
 */
__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;

#ifdef CONFIG_X86_64
static DEFINE_PER_CPU(unsigned char, is_idle);
static ATOMIC_NOTIFIER_HEAD(idle_notifier);

void idle_notifier_register(struct notifier_block *n)
{
	atomic_notifier_chain_register(&idle_notifier, n);
}
EXPORT_SYMBOL_GPL(idle_notifier_register);

void idle_notifier_unregister(struct notifier_block *n)
{
	atomic_notifier_chain_unregister(&idle_notifier, n);
}
EXPORT_SYMBOL_GPL(idle_notifier_unregister);
#endif

struct kmem_cache *task_xstate_cachep;
EXPORT_SYMBOL_GPL(task_xstate_cachep);

/*
 * this gets called so that we can store lazy state into memory and copy the
 * current task into the new thread.
 */
int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
{
	*dst = *src;

	dst->thread.fpu_counter = 0;
	dst->thread.fpu.has_fpu = 0;
	dst->thread.fpu.state = NULL;
	task_disable_lazy_fpu_restore(dst);
	if (tsk_used_math(src)) {
		int err = fpu_alloc(&dst->thread.fpu);
		if (err)
			return err;
		fpu_copy(dst, src);
	}
	return 0;
}

void free_thread_xstate(struct task_struct *tsk)
{
	fpu_free(&tsk->thread.fpu);
}

void arch_release_task_struct(struct task_struct *tsk)
{
	free_thread_xstate(tsk);
}

void arch_task_cache_init(void)
{
        task_xstate_cachep =
        	kmem_cache_create("task_xstate", xstate_size,
				  __alignof__(union thread_xstate),
				  SLAB_PANIC | SLAB_NOTRACK, NULL);
	setup_xstate_comp();
}

/*
 * Free current thread data structures etc..
 */
void exit_thread(void)
{
	struct task_struct *me = current;
	struct thread_struct *t = &me->thread;
	unsigned long *bp = t->io_bitmap_ptr;

	if (bp) {
		struct tss_struct *tss = &per_cpu(init_tss, get_cpu());

		t->io_bitmap_ptr = NULL;
		clear_thread_flag(TIF_IO_BITMAP);
		/*
		 * Careful, clear this in the TSS too:
		 */
		memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
		t->io_bitmap_max = 0;
		put_cpu();
		kfree(bp);
	}

	drop_fpu(me);
}

void flush_thread(void)
{
	struct task_struct *tsk = current;

	flush_ptrace_hw_breakpoint(tsk);
	memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));

	drop_init_fpu(tsk);
	/*
	 * Free the FPU state for non xsave platforms. They get reallocated
	 * lazily at the first use.
	 */
	if (!use_eager_fpu())
		free_thread_xstate(tsk);
	else if (!used_math()) {
		/* kthread execs. TODO: cleanup this horror. */
		if (WARN_ON(init_fpu(current)))
			force_sig(SIGKILL, current);
		math_state_restore();
	}
}

static void hard_disable_TSC(void)
{
	cr4_set_bits(X86_CR4_TSD);
}

void disable_TSC(void)
{
	preempt_disable();
	if (!test_and_set_thread_flag(TIF_NOTSC))
		/*
		 * Must flip the CPU state synchronously with
		 * TIF_NOTSC in the current running context.
		 */
		hard_disable_TSC();
	preempt_enable();
}

static void hard_enable_TSC(void)
{
	cr4_clear_bits(X86_CR4_TSD);
}

static void enable_TSC(void)
{
	preempt_disable();
	if (test_and_clear_thread_flag(TIF_NOTSC))
		/*
		 * Must flip the CPU state synchronously with
		 * TIF_NOTSC in the current running context.
		 */
		hard_enable_TSC();
	preempt_enable();
}

int get_tsc_mode(unsigned long adr)
{
	unsigned int val;

	if (test_thread_flag(TIF_NOTSC))
		val = PR_TSC_SIGSEGV;
	else
		val = PR_TSC_ENABLE;

	return put_user(val, (unsigned int __user *)adr);
}

int set_tsc_mode(unsigned int val)
{
	if (val == PR_TSC_SIGSEGV)
		disable_TSC();
	else if (val == PR_TSC_ENABLE)
		enable_TSC();
	else
		return -EINVAL;

	return 0;
}

void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
		      struct tss_struct *tss)
{
	struct thread_struct *prev, *next;

	prev = &prev_p->thread;
	next = &next_p->thread;

	if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
	    test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
		unsigned long debugctl = get_debugctlmsr();

		debugctl &= ~DEBUGCTLMSR_BTF;
		if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
			debugctl |= DEBUGCTLMSR_BTF;

		update_debugctlmsr(debugctl);
	}

	if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
	    test_tsk_thread_flag(next_p, TIF_NOTSC)) {
		/* prev and next are different */
		if (test_tsk_thread_flag(next_p, TIF_NOTSC))
			hard_disable_TSC();
		else
			hard_enable_TSC();
	}

	if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
		/*
		 * Copy the relevant range of the IO bitmap.
		 * Normally this is 128 bytes or less:
		 */
		memcpy(tss->io_bitmap, next->io_bitmap_ptr,
		       max(prev->io_bitmap_max, next->io_bitmap_max));
	} else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
		/*
		 * Clear any possible leftover bits:
		 */
		memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
	}
	propagate_user_return_notify(prev_p, next_p);
}

/*
 * Idle related variables and functions
 */
unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
EXPORT_SYMBOL(boot_option_idle_override);

static void (*x86_idle)(void);

#ifndef CONFIG_SMP
static inline void play_dead(void)
{
	BUG();
}
#endif

#ifdef CONFIG_X86_64
void enter_idle(void)
{
	this_cpu_write(is_idle, 1);
	atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
}

static void __exit_idle(void)
{
	if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
		return;
	atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
}

/* Called from interrupts to signify idle end */
void exit_idle(void)
{
	/* idle loop has pid 0 */
	if (current->pid)
		return;
	__exit_idle();
}
#endif

void arch_cpu_idle_enter(void)
{
	local_touch_nmi();
	enter_idle();
}

void arch_cpu_idle_exit(void)
{
	__exit_idle();
}

void arch_cpu_idle_dead(void)
{
	play_dead();
}

/*
 * Called from the generic idle code.
 */
void arch_cpu_idle(void)
{
	x86_idle();
}

/*
 * We use this if we don't have any better idle routine..
 */
void default_idle(void)
{
	trace_cpu_idle_rcuidle(1, smp_processor_id());
	safe_halt();
	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
}
#ifdef CONFIG_APM_MODULE
EXPORT_SYMBOL(default_idle);
#endif

#ifdef CONFIG_XEN
bool xen_set_default_idle(void)
{
	bool ret = !!x86_idle;

	x86_idle = default_idle;

	return ret;
}
#endif
void stop_this_cpu(void *dummy)
{
	local_irq_disable();
	/*
	 * Remove this CPU:
	 */
	set_cpu_online(smp_processor_id(), false);
	disable_local_APIC();

	for (;;)
		halt();
}

bool amd_e400_c1e_detected;
EXPORT_SYMBOL(amd_e400_c1e_detected);

static cpumask_var_t amd_e400_c1e_mask;

void amd_e400_remove_cpu(int cpu)
{
	if (amd_e400_c1e_mask != NULL)
		cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
}

/*
 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
 * pending message MSR. If we detect C1E, then we handle it the same
 * way as C3 power states (local apic timer and TSC stop)
 */
static void amd_e400_idle(void)
{
	if (!amd_e400_c1e_detected) {
		u32 lo, hi;

		rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);

		if (lo & K8_INTP_C1E_ACTIVE_MASK) {
			amd_e400_c1e_detected = true;
			if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
				mark_tsc_unstable("TSC halt in AMD C1E");
			pr_info("System has AMD C1E enabled\n");
		}
	}

	if (amd_e400_c1e_detected) {
		int cpu = smp_processor_id();

		if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
			cpumask_set_cpu(cpu, amd_e400_c1e_mask);
			/*
			 * Force broadcast so ACPI can not interfere.
			 */
			clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
					   &cpu);
			pr_info("Switch to broadcast mode on CPU%d\n", cpu);
		}
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);

		default_idle();

		/*
		 * The switch back from broadcast mode needs to be
		 * called with interrupts disabled.
		 */
		local_irq_disable();
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
		local_irq_enable();
	} else
		default_idle();
}

void select_idle_routine(const struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
	if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
		pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
#endif
	if (x86_idle || boot_option_idle_override == IDLE_POLL)
		return;

	if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
		/* E400: APIC timer interrupt does not wake up CPU from C1e */
		pr_info("using AMD E400 aware idle routine\n");
		x86_idle = amd_e400_idle;
	} else
		x86_idle = default_idle;
}

void __init init_amd_e400_c1e_mask(void)
{
	/* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
	if (x86_idle == amd_e400_idle)
		zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
}

static int __init idle_setup(char *str)
{
	if (!str)
		return -EINVAL;

	if (!strcmp(str, "poll")) {
		pr_info("using polling idle threads\n");
		boot_option_idle_override = IDLE_POLL;
		cpu_idle_poll_ctrl(true);
	} else if (!strcmp(str, "halt")) {
		/*
		 * When the boot option of idle=halt is added, halt is
		 * forced to be used for CPU idle. In such case CPU C2/C3
		 * won't be used again.
		 * To continue to load the CPU idle driver, don't touch
		 * the boot_option_idle_override.
		 */
		x86_idle = default_idle;
		boot_option_idle_override = IDLE_HALT;
	} else if (!strcmp(str, "nomwait")) {
		/*
		 * If the boot option of "idle=nomwait" is added,
		 * it means that mwait will be disabled for CPU C2/C3
		 * states. In such case it won't touch the variable
		 * of boot_option_idle_override.
		 */
		boot_option_idle_override = IDLE_NOMWAIT;
	} else
		return -1;

	return 0;
}
early_param("idle", idle_setup);

unsigned long arch_align_stack(unsigned long sp)
{
	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
		sp -= get_random_int() % 8192;
	return sp & ~0xf;
}

unsigned long arch_randomize_brk(struct mm_struct *mm)
{
	unsigned long range_end = mm->brk + 0x02000000;
	return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
}
Commit	Line	Data
c767a54b JP	1	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
c767a54b JP	2
61c4628b SS	3	#include <linux/errno.h>
	4	#include <linux/kernel.h>
	5	#include <linux/mm.h>
	6	#include <linux/smp.h>
389d1fb1	7	#include <linux/prctl.h>
61c4628b SS	8	#include <linux/slab.h>
61c4628b SS	9	#include <linux/sched.h>
7f424a8b PZ	10	#include <linux/module.h>
7f424a8b PZ	11	#include <linux/pm.h>
aa276e1c	12	#include <linux/clockchips.h>
9d62dcdf	13	#include <linux/random.h>
7c68af6e	14	#include <linux/user-return-notifier.h>
814e2c84 AI	15	#include <linux/dmi.h>
814e2c84 AI	16	#include <linux/utsname.h>
90e24014 RW	17	#include <linux/stackprotector.h>
	18	#include <linux/tick.h>
	19	#include <linux/cpuidle.h>
61613521	20	#include <trace/events/power.h>
24f1e32c	21	#include <linux/hw_breakpoint.h>
93789b32	22	#include <asm/cpu.h>
d3ec5cae	23	#include <asm/apic.h>
2c1b284e	24	#include <asm/syscalls.h>
389d1fb1 JF	25	#include <asm/idle.h>
	26	#include <asm/uaccess.h>
	27	#include <asm/i387.h>
1361b83a	28	#include <asm/fpu-internal.h>
66cb5917	29	#include <asm/debugreg.h>
90e24014	30	#include <asm/nmi.h>
375074cc	31	#include <asm/tlbflush.h>
90e24014	32
45046892 TG	33	/*
	34	* per-CPU TSS segments. Threads are completely 'soft' on Linux,
	35	* no more per-task TSS's. The TSS size is kept cacheline-aligned
	36	* so they are allowed to end up in the .data..cacheline_aligned
	37	* section. Since TSS's are completely CPU-local, we want them
	38	* on exact cacheline boundaries, to eliminate cacheline ping-pong.
	39	*/
277d5b40	40	__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;
45046892	41
90e24014 RW	42	#ifdef CONFIG_X86_64
	43	static DEFINE_PER_CPU(unsigned char, is_idle);
	44	static ATOMIC_NOTIFIER_HEAD(idle_notifier);
	45
	46	void idle_notifier_register(struct notifier_block *n)
	47	{
	48	atomic_notifier_chain_register(&idle_notifier, n);
	49	}
	50	EXPORT_SYMBOL_GPL(idle_notifier_register);
	51
	52	void idle_notifier_unregister(struct notifier_block *n)
	53	{
	54	atomic_notifier_chain_unregister(&idle_notifier, n);
	55	}
	56	EXPORT_SYMBOL_GPL(idle_notifier_unregister);
	57	#endif
c1e3b377	58
aa283f49	59	struct kmem_cache *task_xstate_cachep;
5ee481da	60	EXPORT_SYMBOL_GPL(task_xstate_cachep);
61c4628b	61
55ccf3fe SS	62	/*
	63	* this gets called so that we can store lazy state into memory and copy the
	64	* current task into the new thread.
	65	*/
61c4628b SS	66	int arch_dup_task_struct(struct task_struct dst, struct task_struct src)
	67	{
	68	dst = src;
f1853505	69
dc56c0f9	70	dst->thread.fpu_counter = 0;
5e23fee2	71	dst->thread.fpu.has_fpu = 0;
5e23fee2	72	dst->thread.fpu.state = NULL;
6a5fe895	73	task_disable_lazy_fpu_restore(dst);
f1853505 ON	74	if (tsk_used_math(src)) {
	75	int err = fpu_alloc(&dst->thread.fpu);
	76	if (err)
	77	return err;
304bceda	78	fpu_copy(dst, src);
aa283f49	79	}
61c4628b SS	80	return 0;
	81	}
	82
aa283f49	83	void free_thread_xstate(struct task_struct *tsk)
61c4628b	84	{
86603283	85	fpu_free(&tsk->thread.fpu);
aa283f49 SS	86	}
aa283f49 SS	87
38e7c572	88	void arch_release_task_struct(struct task_struct *tsk)
aa283f49	89	{
38e7c572	90	free_thread_xstate(tsk);
61c4628b SS	91	}
	92
	93	void arch_task_cache_init(void)
	94	{
	95	task_xstate_cachep =
	96	kmem_cache_create("task_xstate", xstate_size,
	97	__alignof__(union thread_xstate),
2dff4405	98	SLAB_PANIC \| SLAB_NOTRACK, NULL);
7496d645	99	setup_xstate_comp();
61c4628b	100	}
7f424a8b	101
389d1fb1 JF	102	/*
	103	* Free current thread data structures etc..
	104	*/
	105	void exit_thread(void)
	106	{
	107	struct task_struct *me = current;
	108	struct thread_struct *t = &me->thread;
250981e6	109	unsigned long *bp = t->io_bitmap_ptr;
389d1fb1	110
250981e6	111	if (bp) {
389d1fb1 JF	112	struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
389d1fb1 JF	113
389d1fb1 JF	114	t->io_bitmap_ptr = NULL;
	115	clear_thread_flag(TIF_IO_BITMAP);
	116	/*
	117	* Careful, clear this in the TSS too:
	118	*/
	119	memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
	120	t->io_bitmap_max = 0;
	121	put_cpu();
250981e6	122	kfree(bp);
389d1fb1	123	}
1dcc8d7b SS	124
1dcc8d7b SS	125	drop_fpu(me);
389d1fb1 JF	126	}
	127
	128	void flush_thread(void)
	129	{
	130	struct task_struct *tsk = current;
	131
24f1e32c	132	flush_ptrace_hw_breakpoint(tsk);
389d1fb1	133	memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
110d7f75	134
304bceda SS	135	drop_init_fpu(tsk);
	136	/*
	137	* Free the FPU state for non xsave platforms. They get reallocated
	138	* lazily at the first use.
	139	*/
5d2bd700	140	if (!use_eager_fpu())
304bceda	141	free_thread_xstate(tsk);
110d7f75 ON	142	else if (!used_math()) {
	143	/* kthread execs. TODO: cleanup this horror. */
	144	if (WARN_ON(init_fpu(current)))
	145	force_sig(SIGKILL, current);
	146	math_state_restore();
	147	}
389d1fb1 JF	148	}
	149
	150	static void hard_disable_TSC(void)
	151	{
375074cc	152	cr4_set_bits(X86_CR4_TSD);
389d1fb1 JF	153	}
	154
	155	void disable_TSC(void)
	156	{
	157	preempt_disable();
	158	if (!test_and_set_thread_flag(TIF_NOTSC))
	159	/*
	160	* Must flip the CPU state synchronously with
	161	* TIF_NOTSC in the current running context.
	162	*/
	163	hard_disable_TSC();
	164	preempt_enable();
	165	}
	166
	167	static void hard_enable_TSC(void)
	168	{
375074cc	169	cr4_clear_bits(X86_CR4_TSD);
389d1fb1 JF	170	}
	171
	172	static void enable_TSC(void)
	173	{
	174	preempt_disable();
	175	if (test_and_clear_thread_flag(TIF_NOTSC))
	176	/*
	177	* Must flip the CPU state synchronously with
	178	* TIF_NOTSC in the current running context.
	179	*/
	180	hard_enable_TSC();
	181	preempt_enable();
	182	}
	183
	184	int get_tsc_mode(unsigned long adr)
	185	{
	186	unsigned int val;
	187
	188	if (test_thread_flag(TIF_NOTSC))
	189	val = PR_TSC_SIGSEGV;
	190	else
	191	val = PR_TSC_ENABLE;
	192
	193	return put_user(val, (unsigned int __user *)adr);
	194	}
	195
	196	int set_tsc_mode(unsigned int val)
	197	{
	198	if (val == PR_TSC_SIGSEGV)
	199	disable_TSC();
	200	else if (val == PR_TSC_ENABLE)
	201	enable_TSC();
	202	else
	203	return -EINVAL;
	204
	205	return 0;
	206	}
	207
	208	void __switch_to_xtra(struct task_struct prev_p, struct task_struct next_p,
	209	struct tss_struct *tss)
	210	{
	211	struct thread_struct prev, next;
	212
	213	prev = &prev_p->thread;
	214	next = &next_p->thread;
	215
ea8e61b7 PZ	216	if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
	217	test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
	218	unsigned long debugctl = get_debugctlmsr();
	219
	220	debugctl &= ~DEBUGCTLMSR_BTF;
	221	if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
	222	debugctl \|= DEBUGCTLMSR_BTF;
	223
	224	update_debugctlmsr(debugctl);
	225	}
389d1fb1	226
389d1fb1 JF	227	if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
	228	test_tsk_thread_flag(next_p, TIF_NOTSC)) {
	229	/* prev and next are different */
	230	if (test_tsk_thread_flag(next_p, TIF_NOTSC))
	231	hard_disable_TSC();
	232	else
	233	hard_enable_TSC();
	234	}
	235
	236	if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
	237	/*
	238	* Copy the relevant range of the IO bitmap.
	239	* Normally this is 128 bytes or less:
	240	*/
	241	memcpy(tss->io_bitmap, next->io_bitmap_ptr,
	242	max(prev->io_bitmap_max, next->io_bitmap_max));
	243	} else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
	244	/*
	245	* Clear any possible leftover bits:
	246	*/
	247	memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
	248	}
7c68af6e	249	propagate_user_return_notify(prev_p, next_p);
389d1fb1 JF	250	}
389d1fb1 JF	251
00dba564 TG	252	/*
	253	* Idle related variables and functions
	254	*/
d1896049	255	unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
00dba564 TG	256	EXPORT_SYMBOL(boot_option_idle_override);
00dba564 TG	257
a476bda3	258	static void (*x86_idle)(void);
00dba564	259
90e24014 RW	260	#ifndef CONFIG_SMP
	261	static inline void play_dead(void)
	262	{
	263	BUG();
	264	}
	265	#endif
	266
	267	#ifdef CONFIG_X86_64
	268	void enter_idle(void)
	269	{
c6ae41e7	270	this_cpu_write(is_idle, 1);
90e24014 RW	271	atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
	272	}
	273
	274	static void __exit_idle(void)
	275	{
	276	if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
	277	return;
	278	atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
	279	}
	280
	281	/* Called from interrupts to signify idle end */
	282	void exit_idle(void)
	283	{
	284	/* idle loop has pid 0 */
	285	if (current->pid)
	286	return;
	287	__exit_idle();
	288	}
	289	#endif
	290
7d1a9417 TG	291	void arch_cpu_idle_enter(void)
	292	{
	293	local_touch_nmi();
	294	enter_idle();
	295	}
90e24014	296
7d1a9417 TG	297	void arch_cpu_idle_exit(void)
	298	{
	299	__exit_idle();
	300	}
90e24014	301
7d1a9417 TG	302	void arch_cpu_idle_dead(void)
	303	{
	304	play_dead();
	305	}
90e24014	306
7d1a9417 TG	307	/*
	308	* Called from the generic idle code.
	309	*/
	310	void arch_cpu_idle(void)
	311	{
16f8b05a	312	x86_idle();
90e24014 RW	313	}
90e24014 RW	314
00dba564	315	/*
7d1a9417	316	* We use this if we don't have any better idle routine..
00dba564 TG	317	*/
	318	void default_idle(void)
	319	{
4d0e42cc	320	trace_cpu_idle_rcuidle(1, smp_processor_id());
7d1a9417	321	safe_halt();
4d0e42cc	322	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
00dba564	323	}
60b8b1de	324	#ifdef CONFIG_APM_MODULE
00dba564 TG	325	EXPORT_SYMBOL(default_idle);
	326	#endif
	327
6a377ddc LB	328	#ifdef CONFIG_XEN
6a377ddc LB	329	bool xen_set_default_idle(void)
e5fd47bf	330	{
a476bda3	331	bool ret = !!x86_idle;
e5fd47bf	332
a476bda3	333	x86_idle = default_idle;
e5fd47bf KRW	334
	335	return ret;
	336	}
6a377ddc	337	#endif
d3ec5cae IV	338	void stop_this_cpu(void *dummy)
	339	{
	340	local_irq_disable();
	341	/*
	342	* Remove this CPU:
	343	*/
4f062896	344	set_cpu_online(smp_processor_id(), false);
d3ec5cae IV	345	disable_local_APIC();
d3ec5cae IV	346
27be4570 LB	347	for (;;)
27be4570 LB	348	halt();
7f424a8b PZ	349	}
7f424a8b PZ	350
02c68a02 LB	351	bool amd_e400_c1e_detected;
02c68a02 LB	352	EXPORT_SYMBOL(amd_e400_c1e_detected);
aa276e1c	353
02c68a02	354	static cpumask_var_t amd_e400_c1e_mask;
4faac97d	355
02c68a02	356	void amd_e400_remove_cpu(int cpu)
4faac97d	357	{
02c68a02 LB	358	if (amd_e400_c1e_mask != NULL)
02c68a02 LB	359	cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
4faac97d TG	360	}
4faac97d TG	361
aa276e1c	362	/*
02c68a02	363	* AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
aa276e1c TG	364	* pending message MSR. If we detect C1E, then we handle it the same
	365	* way as C3 power states (local apic timer and TSC stop)
	366	*/
02c68a02	367	static void amd_e400_idle(void)
aa276e1c	368	{
02c68a02	369	if (!amd_e400_c1e_detected) {
aa276e1c TG	370	u32 lo, hi;
	371
	372	rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
e8c534ec	373
aa276e1c	374	if (lo & K8_INTP_C1E_ACTIVE_MASK) {
02c68a02	375	amd_e400_c1e_detected = true;
40fb1715	376	if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
09bfeea1	377	mark_tsc_unstable("TSC halt in AMD C1E");
c767a54b	378	pr_info("System has AMD C1E enabled\n");
aa276e1c TG	379	}
	380	}
	381
02c68a02	382	if (amd_e400_c1e_detected) {
aa276e1c TG	383	int cpu = smp_processor_id();
aa276e1c TG	384
02c68a02 LB	385	if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
02c68a02 LB	386	cpumask_set_cpu(cpu, amd_e400_c1e_mask);
0beefa20	387	/*
f833bab8	388	* Force broadcast so ACPI can not interfere.
0beefa20	389	*/
aa276e1c TG	390	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
aa276e1c TG	391	&cpu);
c767a54b	392	pr_info("Switch to broadcast mode on CPU%d\n", cpu);
aa276e1c TG	393	}
aa276e1c TG	394	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
0beefa20	395
aa276e1c	396	default_idle();
0beefa20 TG	397
	398	/*
	399	* The switch back from broadcast mode needs to be
	400	* called with interrupts disabled.
	401	*/
ea811747 PZ	402	local_irq_disable();
	403	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
	404	local_irq_enable();
aa276e1c TG	405	} else
	406	default_idle();
	407	}
	408
148f9bb8	409	void select_idle_routine(const struct cpuinfo_x86 *c)
7f424a8b	410	{
3e5095d1	411	#ifdef CONFIG_SMP
7d1a9417	412	if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
c767a54b	413	pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
7f424a8b	414	#endif
7d1a9417	415	if (x86_idle \|\| boot_option_idle_override == IDLE_POLL)
6ddd2a27 TG	416	return;
6ddd2a27 TG	417
7d7dc116	418	if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
9d8888c2	419	/* E400: APIC timer interrupt does not wake up CPU from C1e */
c767a54b	420	pr_info("using AMD E400 aware idle routine\n");
a476bda3	421	x86_idle = amd_e400_idle;
6ddd2a27	422	} else
a476bda3	423	x86_idle = default_idle;
7f424a8b PZ	424	}
7f424a8b PZ	425
02c68a02	426	void __init init_amd_e400_c1e_mask(void)
30e1e6d1	427	{
02c68a02	428	/* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
a476bda3	429	if (x86_idle == amd_e400_idle)
02c68a02	430	zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
30e1e6d1 RR	431	}
30e1e6d1 RR	432
7f424a8b PZ	433	static int __init idle_setup(char *str)
7f424a8b PZ	434	{
ab6bc3e3 CG	435	if (!str)
	436	return -EINVAL;
	437
7f424a8b	438	if (!strcmp(str, "poll")) {
c767a54b	439	pr_info("using polling idle threads\n");
d1896049	440	boot_option_idle_override = IDLE_POLL;
7d1a9417	441	cpu_idle_poll_ctrl(true);
d1896049	442	} else if (!strcmp(str, "halt")) {
c1e3b377 ZY	443	/*
	444	* When the boot option of idle=halt is added, halt is
	445	* forced to be used for CPU idle. In such case CPU C2/C3
	446	* won't be used again.
	447	* To continue to load the CPU idle driver, don't touch
	448	* the boot_option_idle_override.
	449	*/
a476bda3	450	x86_idle = default_idle;
d1896049	451	boot_option_idle_override = IDLE_HALT;
da5e09a1 ZY	452	} else if (!strcmp(str, "nomwait")) {
	453	/*
	454	* If the boot option of "idle=nomwait" is added,
	455	* it means that mwait will be disabled for CPU C2/C3
	456	* states. In such case it won't touch the variable
	457	* of boot_option_idle_override.
	458	*/
d1896049	459	boot_option_idle_override = IDLE_NOMWAIT;
c1e3b377	460	} else
7f424a8b PZ	461	return -1;
7f424a8b PZ	462
7f424a8b PZ	463	return 0;
	464	}
	465	early_param("idle", idle_setup);
	466
9d62dcdf AW	467	unsigned long arch_align_stack(unsigned long sp)
	468	{
	469	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
	470	sp -= get_random_int() % 8192;
	471	return sp & ~0xf;
	472	}
	473
	474	unsigned long arch_randomize_brk(struct mm_struct *mm)
	475	{
	476	unsigned long range_end = mm->brk + 0x02000000;
	477	return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
	478	}
	479