Commit | Line | Data |
---|---|---|
61c4628b SS |
1 | #include <linux/errno.h> |
2 | #include <linux/kernel.h> | |
3 | #include <linux/mm.h> | |
4 | #include <linux/smp.h> | |
389d1fb1 | 5 | #include <linux/prctl.h> |
61c4628b SS |
6 | #include <linux/slab.h> |
7 | #include <linux/sched.h> | |
7f424a8b PZ |
8 | #include <linux/module.h> |
9 | #include <linux/pm.h> | |
aa276e1c | 10 | #include <linux/clockchips.h> |
9d62dcdf | 11 | #include <linux/random.h> |
7c68af6e | 12 | #include <linux/user-return-notifier.h> |
814e2c84 AI |
13 | #include <linux/dmi.h> |
14 | #include <linux/utsname.h> | |
90e24014 RW |
15 | #include <linux/stackprotector.h> |
16 | #include <linux/tick.h> | |
17 | #include <linux/cpuidle.h> | |
61613521 | 18 | #include <trace/events/power.h> |
24f1e32c | 19 | #include <linux/hw_breakpoint.h> |
93789b32 | 20 | #include <asm/cpu.h> |
d3ec5cae | 21 | #include <asm/apic.h> |
2c1b284e | 22 | #include <asm/syscalls.h> |
389d1fb1 JF |
23 | #include <asm/idle.h> |
24 | #include <asm/uaccess.h> | |
25 | #include <asm/i387.h> | |
1361b83a | 26 | #include <asm/fpu-internal.h> |
66cb5917 | 27 | #include <asm/debugreg.h> |
90e24014 RW |
28 | #include <asm/nmi.h> |
29 | ||
45046892 TG |
30 | /* |
31 | * per-CPU TSS segments. Threads are completely 'soft' on Linux, | |
32 | * no more per-task TSS's. The TSS size is kept cacheline-aligned | |
33 | * so they are allowed to end up in the .data..cacheline_aligned | |
34 | * section. Since TSS's are completely CPU-local, we want them | |
35 | * on exact cacheline boundaries, to eliminate cacheline ping-pong. | |
36 | */ | |
37 | DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS; | |
38 | ||
90e24014 RW |
39 | #ifdef CONFIG_X86_64 |
40 | static DEFINE_PER_CPU(unsigned char, is_idle); | |
41 | static ATOMIC_NOTIFIER_HEAD(idle_notifier); | |
42 | ||
43 | void idle_notifier_register(struct notifier_block *n) | |
44 | { | |
45 | atomic_notifier_chain_register(&idle_notifier, n); | |
46 | } | |
47 | EXPORT_SYMBOL_GPL(idle_notifier_register); | |
48 | ||
49 | void idle_notifier_unregister(struct notifier_block *n) | |
50 | { | |
51 | atomic_notifier_chain_unregister(&idle_notifier, n); | |
52 | } | |
53 | EXPORT_SYMBOL_GPL(idle_notifier_unregister); | |
54 | #endif | |
c1e3b377 | 55 | |
aa283f49 | 56 | struct kmem_cache *task_xstate_cachep; |
5ee481da | 57 | EXPORT_SYMBOL_GPL(task_xstate_cachep); |
61c4628b SS |
58 | |
59 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) | |
60 | { | |
86603283 AK |
61 | int ret; |
62 | ||
61c4628b | 63 | *dst = *src; |
86603283 AK |
64 | if (fpu_allocated(&src->thread.fpu)) { |
65 | memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu)); | |
66 | ret = fpu_alloc(&dst->thread.fpu); | |
67 | if (ret) | |
68 | return ret; | |
69 | fpu_copy(&dst->thread.fpu, &src->thread.fpu); | |
aa283f49 | 70 | } |
61c4628b SS |
71 | return 0; |
72 | } | |
73 | ||
aa283f49 | 74 | void free_thread_xstate(struct task_struct *tsk) |
61c4628b | 75 | { |
86603283 | 76 | fpu_free(&tsk->thread.fpu); |
aa283f49 SS |
77 | } |
78 | ||
aa283f49 SS |
79 | void free_thread_info(struct thread_info *ti) |
80 | { | |
81 | free_thread_xstate(ti->task); | |
c812d8f7 | 82 | free_pages((unsigned long)ti, THREAD_ORDER); |
61c4628b SS |
83 | } |
84 | ||
85 | void arch_task_cache_init(void) | |
86 | { | |
87 | task_xstate_cachep = | |
88 | kmem_cache_create("task_xstate", xstate_size, | |
89 | __alignof__(union thread_xstate), | |
2dff4405 | 90 | SLAB_PANIC | SLAB_NOTRACK, NULL); |
61c4628b | 91 | } |
7f424a8b | 92 | |
389d1fb1 JF |
93 | /* |
94 | * Free current thread data structures etc.. | |
95 | */ | |
96 | void exit_thread(void) | |
97 | { | |
98 | struct task_struct *me = current; | |
99 | struct thread_struct *t = &me->thread; | |
250981e6 | 100 | unsigned long *bp = t->io_bitmap_ptr; |
389d1fb1 | 101 | |
250981e6 | 102 | if (bp) { |
389d1fb1 JF |
103 | struct tss_struct *tss = &per_cpu(init_tss, get_cpu()); |
104 | ||
389d1fb1 JF |
105 | t->io_bitmap_ptr = NULL; |
106 | clear_thread_flag(TIF_IO_BITMAP); | |
107 | /* | |
108 | * Careful, clear this in the TSS too: | |
109 | */ | |
110 | memset(tss->io_bitmap, 0xff, t->io_bitmap_max); | |
111 | t->io_bitmap_max = 0; | |
112 | put_cpu(); | |
250981e6 | 113 | kfree(bp); |
389d1fb1 | 114 | } |
389d1fb1 JF |
115 | } |
116 | ||
3bef4447 BG |
117 | void show_regs(struct pt_regs *regs) |
118 | { | |
119 | show_registers(regs); | |
e8e999cf | 120 | show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs), 0); |
3bef4447 BG |
121 | } |
122 | ||
814e2c84 AI |
123 | void show_regs_common(void) |
124 | { | |
84e383b3 | 125 | const char *vendor, *product, *board; |
814e2c84 | 126 | |
84e383b3 NC |
127 | vendor = dmi_get_system_info(DMI_SYS_VENDOR); |
128 | if (!vendor) | |
129 | vendor = ""; | |
a1884b8e AI |
130 | product = dmi_get_system_info(DMI_PRODUCT_NAME); |
131 | if (!product) | |
132 | product = ""; | |
814e2c84 | 133 | |
84e383b3 NC |
134 | /* Board Name is optional */ |
135 | board = dmi_get_system_info(DMI_BOARD_NAME); | |
136 | ||
d015a092 | 137 | printk(KERN_CONT "\n"); |
84e383b3 | 138 | printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s", |
814e2c84 AI |
139 | current->pid, current->comm, print_tainted(), |
140 | init_utsname()->release, | |
141 | (int)strcspn(init_utsname()->version, " "), | |
84e383b3 | 142 | init_utsname()->version); |
fd8fa4d3 JB |
143 | printk(KERN_CONT " %s %s", vendor, product); |
144 | if (board) | |
145 | printk(KERN_CONT "/%s", board); | |
84e383b3 | 146 | printk(KERN_CONT "\n"); |
814e2c84 AI |
147 | } |
148 | ||
389d1fb1 JF |
149 | void flush_thread(void) |
150 | { | |
151 | struct task_struct *tsk = current; | |
152 | ||
24f1e32c | 153 | flush_ptrace_hw_breakpoint(tsk); |
389d1fb1 JF |
154 | memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array)); |
155 | /* | |
156 | * Forget coprocessor state.. | |
157 | */ | |
158 | tsk->fpu_counter = 0; | |
159 | clear_fpu(tsk); | |
160 | clear_used_math(); | |
161 | } | |
162 | ||
163 | static void hard_disable_TSC(void) | |
164 | { | |
165 | write_cr4(read_cr4() | X86_CR4_TSD); | |
166 | } | |
167 | ||
168 | void disable_TSC(void) | |
169 | { | |
170 | preempt_disable(); | |
171 | if (!test_and_set_thread_flag(TIF_NOTSC)) | |
172 | /* | |
173 | * Must flip the CPU state synchronously with | |
174 | * TIF_NOTSC in the current running context. | |
175 | */ | |
176 | hard_disable_TSC(); | |
177 | preempt_enable(); | |
178 | } | |
179 | ||
180 | static void hard_enable_TSC(void) | |
181 | { | |
182 | write_cr4(read_cr4() & ~X86_CR4_TSD); | |
183 | } | |
184 | ||
185 | static void enable_TSC(void) | |
186 | { | |
187 | preempt_disable(); | |
188 | if (test_and_clear_thread_flag(TIF_NOTSC)) | |
189 | /* | |
190 | * Must flip the CPU state synchronously with | |
191 | * TIF_NOTSC in the current running context. | |
192 | */ | |
193 | hard_enable_TSC(); | |
194 | preempt_enable(); | |
195 | } | |
196 | ||
197 | int get_tsc_mode(unsigned long adr) | |
198 | { | |
199 | unsigned int val; | |
200 | ||
201 | if (test_thread_flag(TIF_NOTSC)) | |
202 | val = PR_TSC_SIGSEGV; | |
203 | else | |
204 | val = PR_TSC_ENABLE; | |
205 | ||
206 | return put_user(val, (unsigned int __user *)adr); | |
207 | } | |
208 | ||
209 | int set_tsc_mode(unsigned int val) | |
210 | { | |
211 | if (val == PR_TSC_SIGSEGV) | |
212 | disable_TSC(); | |
213 | else if (val == PR_TSC_ENABLE) | |
214 | enable_TSC(); | |
215 | else | |
216 | return -EINVAL; | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
221 | void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p, | |
222 | struct tss_struct *tss) | |
223 | { | |
224 | struct thread_struct *prev, *next; | |
225 | ||
226 | prev = &prev_p->thread; | |
227 | next = &next_p->thread; | |
228 | ||
ea8e61b7 PZ |
229 | if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^ |
230 | test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) { | |
231 | unsigned long debugctl = get_debugctlmsr(); | |
232 | ||
233 | debugctl &= ~DEBUGCTLMSR_BTF; | |
234 | if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) | |
235 | debugctl |= DEBUGCTLMSR_BTF; | |
236 | ||
237 | update_debugctlmsr(debugctl); | |
238 | } | |
389d1fb1 | 239 | |
389d1fb1 JF |
240 | if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^ |
241 | test_tsk_thread_flag(next_p, TIF_NOTSC)) { | |
242 | /* prev and next are different */ | |
243 | if (test_tsk_thread_flag(next_p, TIF_NOTSC)) | |
244 | hard_disable_TSC(); | |
245 | else | |
246 | hard_enable_TSC(); | |
247 | } | |
248 | ||
249 | if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) { | |
250 | /* | |
251 | * Copy the relevant range of the IO bitmap. | |
252 | * Normally this is 128 bytes or less: | |
253 | */ | |
254 | memcpy(tss->io_bitmap, next->io_bitmap_ptr, | |
255 | max(prev->io_bitmap_max, next->io_bitmap_max)); | |
256 | } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) { | |
257 | /* | |
258 | * Clear any possible leftover bits: | |
259 | */ | |
260 | memset(tss->io_bitmap, 0xff, prev->io_bitmap_max); | |
261 | } | |
7c68af6e | 262 | propagate_user_return_notify(prev_p, next_p); |
389d1fb1 JF |
263 | } |
264 | ||
265 | int sys_fork(struct pt_regs *regs) | |
266 | { | |
267 | return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL); | |
268 | } | |
269 | ||
270 | /* | |
271 | * This is trivial, and on the face of it looks like it | |
272 | * could equally well be done in user mode. | |
273 | * | |
274 | * Not so, for quite unobvious reasons - register pressure. | |
275 | * In user mode vfork() cannot have a stack frame, and if | |
276 | * done by calling the "clone()" system call directly, you | |
277 | * do not have enough call-clobbered registers to hold all | |
278 | * the information you need. | |
279 | */ | |
280 | int sys_vfork(struct pt_regs *regs) | |
281 | { | |
282 | return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0, | |
283 | NULL, NULL); | |
284 | } | |
285 | ||
f839bbc5 BG |
286 | long |
287 | sys_clone(unsigned long clone_flags, unsigned long newsp, | |
288 | void __user *parent_tid, void __user *child_tid, struct pt_regs *regs) | |
289 | { | |
290 | if (!newsp) | |
291 | newsp = regs->sp; | |
292 | return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid); | |
293 | } | |
294 | ||
df59e7bf BG |
295 | /* |
296 | * This gets run with %si containing the | |
297 | * function to call, and %di containing | |
298 | * the "args". | |
299 | */ | |
300 | extern void kernel_thread_helper(void); | |
301 | ||
302 | /* | |
303 | * Create a kernel thread | |
304 | */ | |
305 | int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags) | |
306 | { | |
307 | struct pt_regs regs; | |
308 | ||
309 | memset(®s, 0, sizeof(regs)); | |
310 | ||
311 | regs.si = (unsigned long) fn; | |
312 | regs.di = (unsigned long) arg; | |
313 | ||
314 | #ifdef CONFIG_X86_32 | |
315 | regs.ds = __USER_DS; | |
316 | regs.es = __USER_DS; | |
317 | regs.fs = __KERNEL_PERCPU; | |
318 | regs.gs = __KERNEL_STACK_CANARY; | |
864a0922 CG |
319 | #else |
320 | regs.ss = __KERNEL_DS; | |
df59e7bf BG |
321 | #endif |
322 | ||
323 | regs.orig_ax = -1; | |
324 | regs.ip = (unsigned long) kernel_thread_helper; | |
325 | regs.cs = __KERNEL_CS | get_kernel_rpl(); | |
1cf8343f | 326 | regs.flags = X86_EFLAGS_IF | X86_EFLAGS_BIT1; |
df59e7bf BG |
327 | |
328 | /* Ok, create the new process.. */ | |
329 | return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL); | |
330 | } | |
331 | EXPORT_SYMBOL(kernel_thread); | |
389d1fb1 | 332 | |
11cf88bd BG |
333 | /* |
334 | * sys_execve() executes a new program. | |
335 | */ | |
d7627467 DH |
336 | long sys_execve(const char __user *name, |
337 | const char __user *const __user *argv, | |
338 | const char __user *const __user *envp, struct pt_regs *regs) | |
11cf88bd BG |
339 | { |
340 | long error; | |
341 | char *filename; | |
342 | ||
343 | filename = getname(name); | |
344 | error = PTR_ERR(filename); | |
345 | if (IS_ERR(filename)) | |
346 | return error; | |
347 | error = do_execve(filename, argv, envp, regs); | |
348 | ||
349 | #ifdef CONFIG_X86_32 | |
350 | if (error == 0) { | |
351 | /* Make sure we don't return using sysenter.. */ | |
352 | set_thread_flag(TIF_IRET); | |
353 | } | |
354 | #endif | |
355 | ||
356 | putname(filename); | |
357 | return error; | |
358 | } | |
389d1fb1 | 359 | |
00dba564 TG |
360 | /* |
361 | * Idle related variables and functions | |
362 | */ | |
d1896049 | 363 | unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE; |
00dba564 TG |
364 | EXPORT_SYMBOL(boot_option_idle_override); |
365 | ||
366 | /* | |
367 | * Powermanagement idle function, if any.. | |
368 | */ | |
369 | void (*pm_idle)(void); | |
60b8b1de | 370 | #ifdef CONFIG_APM_MODULE |
00dba564 | 371 | EXPORT_SYMBOL(pm_idle); |
06ae40ce | 372 | #endif |
00dba564 | 373 | |
00dba564 TG |
374 | static inline int hlt_use_halt(void) |
375 | { | |
376 | return 1; | |
377 | } | |
00dba564 | 378 | |
90e24014 RW |
379 | #ifndef CONFIG_SMP |
380 | static inline void play_dead(void) | |
381 | { | |
382 | BUG(); | |
383 | } | |
384 | #endif | |
385 | ||
386 | #ifdef CONFIG_X86_64 | |
387 | void enter_idle(void) | |
388 | { | |
389 | percpu_write(is_idle, 1); | |
390 | atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL); | |
391 | } | |
392 | ||
393 | static void __exit_idle(void) | |
394 | { | |
395 | if (x86_test_and_clear_bit_percpu(0, is_idle) == 0) | |
396 | return; | |
397 | atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL); | |
398 | } | |
399 | ||
400 | /* Called from interrupts to signify idle end */ | |
401 | void exit_idle(void) | |
402 | { | |
403 | /* idle loop has pid 0 */ | |
404 | if (current->pid) | |
405 | return; | |
406 | __exit_idle(); | |
407 | } | |
408 | #endif | |
409 | ||
410 | /* | |
411 | * The idle thread. There's no useful work to be | |
412 | * done, so just try to conserve power and have a | |
413 | * low exit latency (ie sit in a loop waiting for | |
414 | * somebody to say that they'd like to reschedule) | |
415 | */ | |
416 | void cpu_idle(void) | |
417 | { | |
418 | /* | |
419 | * If we're the non-boot CPU, nothing set the stack canary up | |
420 | * for us. CPU0 already has it initialized but no harm in | |
421 | * doing it again. This is a good place for updating it, as | |
422 | * we wont ever return from this function (so the invalid | |
423 | * canaries already on the stack wont ever trigger). | |
424 | */ | |
425 | boot_init_stack_canary(); | |
426 | current_thread_info()->status |= TS_POLLING; | |
427 | ||
428 | while (1) { | |
429 | tick_nohz_idle_enter(); | |
430 | ||
431 | while (!need_resched()) { | |
432 | rmb(); | |
433 | ||
434 | if (cpu_is_offline(smp_processor_id())) | |
435 | play_dead(); | |
436 | ||
437 | /* | |
438 | * Idle routines should keep interrupts disabled | |
439 | * from here on, until they go to idle. | |
440 | * Otherwise, idle callbacks can misfire. | |
441 | */ | |
442 | local_touch_nmi(); | |
443 | local_irq_disable(); | |
444 | ||
445 | enter_idle(); | |
446 | ||
447 | /* Don't trace irqs off for idle */ | |
448 | stop_critical_timings(); | |
449 | ||
450 | /* enter_idle() needs rcu for notifiers */ | |
451 | rcu_idle_enter(); | |
452 | ||
453 | if (cpuidle_idle_call()) | |
454 | pm_idle(); | |
455 | ||
456 | rcu_idle_exit(); | |
457 | start_critical_timings(); | |
458 | ||
459 | /* In many cases the interrupt that ended idle | |
460 | has already called exit_idle. But some idle | |
461 | loops can be woken up without interrupt. */ | |
462 | __exit_idle(); | |
463 | } | |
464 | ||
465 | tick_nohz_idle_exit(); | |
466 | preempt_enable_no_resched(); | |
467 | schedule(); | |
468 | preempt_disable(); | |
469 | } | |
470 | } | |
471 | ||
00dba564 TG |
472 | /* |
473 | * We use this if we don't have any better | |
474 | * idle routine.. | |
475 | */ | |
476 | void default_idle(void) | |
477 | { | |
478 | if (hlt_use_halt()) { | |
48454650 SR |
479 | trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id()); |
480 | trace_cpu_idle_rcuidle(1, smp_processor_id()); | |
00dba564 TG |
481 | current_thread_info()->status &= ~TS_POLLING; |
482 | /* | |
483 | * TS_POLLING-cleared state must be visible before we | |
484 | * test NEED_RESCHED: | |
485 | */ | |
486 | smp_mb(); | |
487 | ||
488 | if (!need_resched()) | |
489 | safe_halt(); /* enables interrupts racelessly */ | |
490 | else | |
491 | local_irq_enable(); | |
492 | current_thread_info()->status |= TS_POLLING; | |
48454650 SR |
493 | trace_power_end_rcuidle(smp_processor_id()); |
494 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); | |
00dba564 TG |
495 | } else { |
496 | local_irq_enable(); | |
497 | /* loop is done by the caller */ | |
498 | cpu_relax(); | |
499 | } | |
500 | } | |
60b8b1de | 501 | #ifdef CONFIG_APM_MODULE |
00dba564 TG |
502 | EXPORT_SYMBOL(default_idle); |
503 | #endif | |
504 | ||
e5fd47bf KRW |
505 | bool set_pm_idle_to_default(void) |
506 | { | |
507 | bool ret = !!pm_idle; | |
508 | ||
509 | pm_idle = default_idle; | |
510 | ||
511 | return ret; | |
512 | } | |
d3ec5cae IV |
513 | void stop_this_cpu(void *dummy) |
514 | { | |
515 | local_irq_disable(); | |
516 | /* | |
517 | * Remove this CPU: | |
518 | */ | |
4f062896 | 519 | set_cpu_online(smp_processor_id(), false); |
d3ec5cae IV |
520 | disable_local_APIC(); |
521 | ||
522 | for (;;) { | |
523 | if (hlt_works(smp_processor_id())) | |
524 | halt(); | |
525 | } | |
526 | } | |
527 | ||
7f424a8b PZ |
528 | /* Default MONITOR/MWAIT with no hints, used for default C1 state */ |
529 | static void mwait_idle(void) | |
530 | { | |
531 | if (!need_resched()) { | |
48454650 SR |
532 | trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id()); |
533 | trace_cpu_idle_rcuidle(1, smp_processor_id()); | |
349c004e | 534 | if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR)) |
e736ad54 PV |
535 | clflush((void *)¤t_thread_info()->flags); |
536 | ||
7f424a8b PZ |
537 | __monitor((void *)¤t_thread_info()->flags, 0, 0); |
538 | smp_mb(); | |
539 | if (!need_resched()) | |
540 | __sti_mwait(0, 0); | |
541 | else | |
542 | local_irq_enable(); | |
48454650 SR |
543 | trace_power_end_rcuidle(smp_processor_id()); |
544 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); | |
7f424a8b PZ |
545 | } else |
546 | local_irq_enable(); | |
547 | } | |
548 | ||
7f424a8b PZ |
549 | /* |
550 | * On SMP it's slightly faster (but much more power-consuming!) | |
551 | * to poll the ->work.need_resched flag instead of waiting for the | |
552 | * cross-CPU IPI to arrive. Use this option with caution. | |
553 | */ | |
554 | static void poll_idle(void) | |
555 | { | |
48454650 SR |
556 | trace_power_start_rcuidle(POWER_CSTATE, 0, smp_processor_id()); |
557 | trace_cpu_idle_rcuidle(0, smp_processor_id()); | |
7f424a8b | 558 | local_irq_enable(); |
2c7e9fd4 JK |
559 | while (!need_resched()) |
560 | cpu_relax(); | |
48454650 SR |
561 | trace_power_end_rcuidle(smp_processor_id()); |
562 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); | |
7f424a8b PZ |
563 | } |
564 | ||
e9623b35 TG |
565 | /* |
566 | * mwait selection logic: | |
567 | * | |
568 | * It depends on the CPU. For AMD CPUs that support MWAIT this is | |
569 | * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings | |
570 | * then depend on a clock divisor and current Pstate of the core. If | |
571 | * all cores of a processor are in halt state (C1) the processor can | |
572 | * enter the C1E (C1 enhanced) state. If mwait is used this will never | |
573 | * happen. | |
574 | * | |
575 | * idle=mwait overrides this decision and forces the usage of mwait. | |
576 | */ | |
09fd4b4e TG |
577 | |
578 | #define MWAIT_INFO 0x05 | |
579 | #define MWAIT_ECX_EXTENDED_INFO 0x01 | |
580 | #define MWAIT_EDX_C1 0xf0 | |
581 | ||
1c9d16e3 | 582 | int mwait_usable(const struct cpuinfo_x86 *c) |
e9623b35 | 583 | { |
09fd4b4e TG |
584 | u32 eax, ebx, ecx, edx; |
585 | ||
d1896049 | 586 | if (boot_option_idle_override == IDLE_FORCE_MWAIT) |
e9623b35 TG |
587 | return 1; |
588 | ||
09fd4b4e TG |
589 | if (c->cpuid_level < MWAIT_INFO) |
590 | return 0; | |
591 | ||
592 | cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx); | |
593 | /* Check, whether EDX has extended info about MWAIT */ | |
594 | if (!(ecx & MWAIT_ECX_EXTENDED_INFO)) | |
595 | return 1; | |
596 | ||
597 | /* | |
598 | * edx enumeratios MONITOR/MWAIT extensions. Check, whether | |
599 | * C1 supports MWAIT | |
600 | */ | |
601 | return (edx & MWAIT_EDX_C1); | |
e9623b35 TG |
602 | } |
603 | ||
02c68a02 LB |
604 | bool amd_e400_c1e_detected; |
605 | EXPORT_SYMBOL(amd_e400_c1e_detected); | |
aa276e1c | 606 | |
02c68a02 | 607 | static cpumask_var_t amd_e400_c1e_mask; |
4faac97d | 608 | |
02c68a02 | 609 | void amd_e400_remove_cpu(int cpu) |
4faac97d | 610 | { |
02c68a02 LB |
611 | if (amd_e400_c1e_mask != NULL) |
612 | cpumask_clear_cpu(cpu, amd_e400_c1e_mask); | |
4faac97d TG |
613 | } |
614 | ||
aa276e1c | 615 | /* |
02c68a02 | 616 | * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt |
aa276e1c TG |
617 | * pending message MSR. If we detect C1E, then we handle it the same |
618 | * way as C3 power states (local apic timer and TSC stop) | |
619 | */ | |
02c68a02 | 620 | static void amd_e400_idle(void) |
aa276e1c | 621 | { |
aa276e1c TG |
622 | if (need_resched()) |
623 | return; | |
624 | ||
02c68a02 | 625 | if (!amd_e400_c1e_detected) { |
aa276e1c TG |
626 | u32 lo, hi; |
627 | ||
628 | rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi); | |
e8c534ec | 629 | |
aa276e1c | 630 | if (lo & K8_INTP_C1E_ACTIVE_MASK) { |
02c68a02 | 631 | amd_e400_c1e_detected = true; |
40fb1715 | 632 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
09bfeea1 AH |
633 | mark_tsc_unstable("TSC halt in AMD C1E"); |
634 | printk(KERN_INFO "System has AMD C1E enabled\n"); | |
aa276e1c TG |
635 | } |
636 | } | |
637 | ||
02c68a02 | 638 | if (amd_e400_c1e_detected) { |
aa276e1c TG |
639 | int cpu = smp_processor_id(); |
640 | ||
02c68a02 LB |
641 | if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) { |
642 | cpumask_set_cpu(cpu, amd_e400_c1e_mask); | |
0beefa20 | 643 | /* |
f833bab8 | 644 | * Force broadcast so ACPI can not interfere. |
0beefa20 | 645 | */ |
aa276e1c TG |
646 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
647 | &cpu); | |
648 | printk(KERN_INFO "Switch to broadcast mode on CPU%d\n", | |
649 | cpu); | |
650 | } | |
651 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | |
0beefa20 | 652 | |
aa276e1c | 653 | default_idle(); |
0beefa20 TG |
654 | |
655 | /* | |
656 | * The switch back from broadcast mode needs to be | |
657 | * called with interrupts disabled. | |
658 | */ | |
659 | local_irq_disable(); | |
660 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); | |
661 | local_irq_enable(); | |
aa276e1c TG |
662 | } else |
663 | default_idle(); | |
664 | } | |
665 | ||
7f424a8b PZ |
666 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) |
667 | { | |
3e5095d1 | 668 | #ifdef CONFIG_SMP |
7f424a8b | 669 | if (pm_idle == poll_idle && smp_num_siblings > 1) { |
d6dd6921 | 670 | printk_once(KERN_WARNING "WARNING: polling idle and HT enabled," |
7f424a8b PZ |
671 | " performance may degrade.\n"); |
672 | } | |
673 | #endif | |
6ddd2a27 TG |
674 | if (pm_idle) |
675 | return; | |
676 | ||
e9623b35 | 677 | if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { |
7f424a8b | 678 | /* |
7f424a8b PZ |
679 | * One CPU supports mwait => All CPUs supports mwait |
680 | */ | |
6ddd2a27 TG |
681 | printk(KERN_INFO "using mwait in idle threads.\n"); |
682 | pm_idle = mwait_idle; | |
9d8888c2 HR |
683 | } else if (cpu_has_amd_erratum(amd_erratum_400)) { |
684 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ | |
02c68a02 LB |
685 | printk(KERN_INFO "using AMD E400 aware idle routine\n"); |
686 | pm_idle = amd_e400_idle; | |
6ddd2a27 TG |
687 | } else |
688 | pm_idle = default_idle; | |
7f424a8b PZ |
689 | } |
690 | ||
02c68a02 | 691 | void __init init_amd_e400_c1e_mask(void) |
30e1e6d1 | 692 | { |
02c68a02 LB |
693 | /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */ |
694 | if (pm_idle == amd_e400_idle) | |
695 | zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL); | |
30e1e6d1 RR |
696 | } |
697 | ||
7f424a8b PZ |
698 | static int __init idle_setup(char *str) |
699 | { | |
ab6bc3e3 CG |
700 | if (!str) |
701 | return -EINVAL; | |
702 | ||
7f424a8b PZ |
703 | if (!strcmp(str, "poll")) { |
704 | printk("using polling idle threads.\n"); | |
705 | pm_idle = poll_idle; | |
d1896049 TR |
706 | boot_option_idle_override = IDLE_POLL; |
707 | } else if (!strcmp(str, "mwait")) { | |
708 | boot_option_idle_override = IDLE_FORCE_MWAIT; | |
af0d6a0a | 709 | WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n"); |
d1896049 | 710 | } else if (!strcmp(str, "halt")) { |
c1e3b377 ZY |
711 | /* |
712 | * When the boot option of idle=halt is added, halt is | |
713 | * forced to be used for CPU idle. In such case CPU C2/C3 | |
714 | * won't be used again. | |
715 | * To continue to load the CPU idle driver, don't touch | |
716 | * the boot_option_idle_override. | |
717 | */ | |
718 | pm_idle = default_idle; | |
d1896049 | 719 | boot_option_idle_override = IDLE_HALT; |
da5e09a1 ZY |
720 | } else if (!strcmp(str, "nomwait")) { |
721 | /* | |
722 | * If the boot option of "idle=nomwait" is added, | |
723 | * it means that mwait will be disabled for CPU C2/C3 | |
724 | * states. In such case it won't touch the variable | |
725 | * of boot_option_idle_override. | |
726 | */ | |
d1896049 | 727 | boot_option_idle_override = IDLE_NOMWAIT; |
c1e3b377 | 728 | } else |
7f424a8b PZ |
729 | return -1; |
730 | ||
7f424a8b PZ |
731 | return 0; |
732 | } | |
733 | early_param("idle", idle_setup); | |
734 | ||
9d62dcdf AW |
735 | unsigned long arch_align_stack(unsigned long sp) |
736 | { | |
737 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
738 | sp -= get_random_int() % 8192; | |
739 | return sp & ~0xf; | |
740 | } | |
741 | ||
742 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
743 | { | |
744 | unsigned long range_end = mm->brk + 0x02000000; | |
745 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
746 | } | |
747 |