[linux-2.6-block.git] / arch / x86 / kernel / process.c

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/prctl.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/clockchips.h>
#include <linux/random.h>
#include <linux/user-return-notifier.h>
#include <linux/dmi.h>
#include <linux/utsname.h>
#include <linux/stackprotector.h>
#include <linux/tick.h>
#include <linux/cpuidle.h>
#include <trace/events/power.h>
#include <linux/hw_breakpoint.h>
#include <asm/cpu.h>
#include <asm/apic.h>
#include <asm/syscalls.h>
#include <asm/idle.h>
#include <asm/uaccess.h>
#include <asm/i387.h>
#include <asm/fpu-internal.h>
#include <asm/debugreg.h>
#include <asm/nmi.h>

/*
 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
 * no more per-task TSS's. The TSS size is kept cacheline-aligned
 * so they are allowed to end up in the .data..cacheline_aligned
 * section. Since TSS's are completely CPU-local, we want them
 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
 */
__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;

#ifdef CONFIG_X86_64
static DEFINE_PER_CPU(unsigned char, is_idle);
static ATOMIC_NOTIFIER_HEAD(idle_notifier);

void idle_notifier_register(struct notifier_block *n)
{
	atomic_notifier_chain_register(&idle_notifier, n);
}
EXPORT_SYMBOL_GPL(idle_notifier_register);

void idle_notifier_unregister(struct notifier_block *n)
{
	atomic_notifier_chain_unregister(&idle_notifier, n);
}
EXPORT_SYMBOL_GPL(idle_notifier_unregister);
#endif

struct kmem_cache *task_xstate_cachep;
EXPORT_SYMBOL_GPL(task_xstate_cachep);

/*
 * this gets called so that we can store lazy state into memory and copy the
 * current task into the new thread.
 */
int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
{
	int ret;

	*dst = *src;
	if (fpu_allocated(&src->thread.fpu)) {
		memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
		ret = fpu_alloc(&dst->thread.fpu);
		if (ret)
			return ret;
		fpu_copy(dst, src);
	}
	return 0;
}

void free_thread_xstate(struct task_struct *tsk)
{
	fpu_free(&tsk->thread.fpu);
}

void arch_release_task_struct(struct task_struct *tsk)
{
	free_thread_xstate(tsk);
}

void arch_task_cache_init(void)
{
        task_xstate_cachep =
        	kmem_cache_create("task_xstate", xstate_size,
				  __alignof__(union thread_xstate),
				  SLAB_PANIC | SLAB_NOTRACK, NULL);
	setup_xstate_comp();
}

/*
 * Free current thread data structures etc..
 */
void exit_thread(void)
{
	struct task_struct *me = current;
	struct thread_struct *t = &me->thread;
	unsigned long *bp = t->io_bitmap_ptr;

	if (bp) {
		struct tss_struct *tss = &per_cpu(init_tss, get_cpu());

		t->io_bitmap_ptr = NULL;
		clear_thread_flag(TIF_IO_BITMAP);
		/*
		 * Careful, clear this in the TSS too:
		 */
		memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
		t->io_bitmap_max = 0;
		put_cpu();
		kfree(bp);
	}

	drop_fpu(me);
}

void flush_thread(void)
{
	struct task_struct *tsk = current;

	flush_ptrace_hw_breakpoint(tsk);
	memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
	drop_init_fpu(tsk);
	/*
	 * Free the FPU state for non xsave platforms. They get reallocated
	 * lazily at the first use.
	 */
	if (!use_eager_fpu())
		free_thread_xstate(tsk);
}

static void hard_disable_TSC(void)
{
	write_cr4(read_cr4() | X86_CR4_TSD);
}

void disable_TSC(void)
{
	preempt_disable();
	if (!test_and_set_thread_flag(TIF_NOTSC))
		/*
		 * Must flip the CPU state synchronously with
		 * TIF_NOTSC in the current running context.
		 */
		hard_disable_TSC();
	preempt_enable();
}

static void hard_enable_TSC(void)
{
	write_cr4(read_cr4() & ~X86_CR4_TSD);
}

static void enable_TSC(void)
{
	preempt_disable();
	if (test_and_clear_thread_flag(TIF_NOTSC))
		/*
		 * Must flip the CPU state synchronously with
		 * TIF_NOTSC in the current running context.
		 */
		hard_enable_TSC();
	preempt_enable();
}

int get_tsc_mode(unsigned long adr)
{
	unsigned int val;

	if (test_thread_flag(TIF_NOTSC))
		val = PR_TSC_SIGSEGV;
	else
		val = PR_TSC_ENABLE;

	return put_user(val, (unsigned int __user *)adr);
}

int set_tsc_mode(unsigned int val)
{
	if (val == PR_TSC_SIGSEGV)
		disable_TSC();
	else if (val == PR_TSC_ENABLE)
		enable_TSC();
	else
		return -EINVAL;

	return 0;
}

void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
		      struct tss_struct *tss)
{
	struct thread_struct *prev, *next;

	prev = &prev_p->thread;
	next = &next_p->thread;

	if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
	    test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
		unsigned long debugctl = get_debugctlmsr();

		debugctl &= ~DEBUGCTLMSR_BTF;
		if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
			debugctl |= DEBUGCTLMSR_BTF;

		update_debugctlmsr(debugctl);
	}

	if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
	    test_tsk_thread_flag(next_p, TIF_NOTSC)) {
		/* prev and next are different */
		if (test_tsk_thread_flag(next_p, TIF_NOTSC))
			hard_disable_TSC();
		else
			hard_enable_TSC();
	}

	if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
		/*
		 * Copy the relevant range of the IO bitmap.
		 * Normally this is 128 bytes or less:
		 */
		memcpy(tss->io_bitmap, next->io_bitmap_ptr,
		       max(prev->io_bitmap_max, next->io_bitmap_max));
	} else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
		/*
		 * Clear any possible leftover bits:
		 */
		memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
	}
	propagate_user_return_notify(prev_p, next_p);
}

/*
 * Idle related variables and functions
 */
unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
EXPORT_SYMBOL(boot_option_idle_override);

static void (*x86_idle)(void);

#ifndef CONFIG_SMP
static inline void play_dead(void)
{
	BUG();
}
#endif

#ifdef CONFIG_X86_64
void enter_idle(void)
{
	this_cpu_write(is_idle, 1);
	atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
}

static void __exit_idle(void)
{
	if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
		return;
	atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
}

/* Called from interrupts to signify idle end */
void exit_idle(void)
{
	/* idle loop has pid 0 */
	if (current->pid)
		return;
	__exit_idle();
}
#endif

void arch_cpu_idle_enter(void)
{
	local_touch_nmi();
	enter_idle();
}

void arch_cpu_idle_exit(void)
{
	__exit_idle();
}

void arch_cpu_idle_dead(void)
{
	play_dead();
}

/*
 * Called from the generic idle code.
 */
void arch_cpu_idle(void)
{
	x86_idle();
}

/*
 * We use this if we don't have any better idle routine..
 */
void default_idle(void)
{
	trace_cpu_idle_rcuidle(1, smp_processor_id());
	safe_halt();
	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
}
#ifdef CONFIG_APM_MODULE
EXPORT_SYMBOL(default_idle);
#endif

#ifdef CONFIG_XEN
bool xen_set_default_idle(void)
{
	bool ret = !!x86_idle;

	x86_idle = default_idle;

	return ret;
}
#endif
void stop_this_cpu(void *dummy)
{
	local_irq_disable();
	/*
	 * Remove this CPU:
	 */
	set_cpu_online(smp_processor_id(), false);
	disable_local_APIC();

	for (;;)
		halt();
}

bool amd_e400_c1e_detected;
EXPORT_SYMBOL(amd_e400_c1e_detected);

static cpumask_var_t amd_e400_c1e_mask;

void amd_e400_remove_cpu(int cpu)
{
	if (amd_e400_c1e_mask != NULL)
		cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
}

/*
 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
 * pending message MSR. If we detect C1E, then we handle it the same
 * way as C3 power states (local apic timer and TSC stop)
 */
static void amd_e400_idle(void)
{
	if (!amd_e400_c1e_detected) {
		u32 lo, hi;

		rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);

		if (lo & K8_INTP_C1E_ACTIVE_MASK) {
			amd_e400_c1e_detected = true;
			if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
				mark_tsc_unstable("TSC halt in AMD C1E");
			pr_info("System has AMD C1E enabled\n");
		}
	}

	if (amd_e400_c1e_detected) {
		int cpu = smp_processor_id();

		if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
			cpumask_set_cpu(cpu, amd_e400_c1e_mask);
			/*
			 * Force broadcast so ACPI can not interfere.
			 */
			clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
					   &cpu);
			pr_info("Switch to broadcast mode on CPU%d\n", cpu);
		}
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);

		default_idle();

		/*
		 * The switch back from broadcast mode needs to be
		 * called with interrupts disabled.
		 */
		local_irq_disable();
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
		local_irq_enable();
	} else
		default_idle();
}

void select_idle_routine(const struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
	if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
		pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
#endif
	if (x86_idle || boot_option_idle_override == IDLE_POLL)
		return;

	if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
		/* E400: APIC timer interrupt does not wake up CPU from C1e */
		pr_info("using AMD E400 aware idle routine\n");
		x86_idle = amd_e400_idle;
	} else
		x86_idle = default_idle;
}

void __init init_amd_e400_c1e_mask(void)
{
	/* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
	if (x86_idle == amd_e400_idle)
		zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
}

static int __init idle_setup(char *str)
{
	if (!str)
		return -EINVAL;

	if (!strcmp(str, "poll")) {
		pr_info("using polling idle threads\n");
		boot_option_idle_override = IDLE_POLL;
		cpu_idle_poll_ctrl(true);
	} else if (!strcmp(str, "halt")) {
		/*
		 * When the boot option of idle=halt is added, halt is
		 * forced to be used for CPU idle. In such case CPU C2/C3
		 * won't be used again.
		 * To continue to load the CPU idle driver, don't touch
		 * the boot_option_idle_override.
		 */
		x86_idle = default_idle;
		boot_option_idle_override = IDLE_HALT;
	} else if (!strcmp(str, "nomwait")) {
		/*
		 * If the boot option of "idle=nomwait" is added,
		 * it means that mwait will be disabled for CPU C2/C3
		 * states. In such case it won't touch the variable
		 * of boot_option_idle_override.
		 */
		boot_option_idle_override = IDLE_NOMWAIT;
	} else
		return -1;

	return 0;
}
early_param("idle", idle_setup);

unsigned long arch_align_stack(unsigned long sp)
{
	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
		sp -= get_random_int() % 8192;
	return sp & ~0xf;
}

unsigned long arch_randomize_brk(struct mm_struct *mm)
{
	unsigned long range_end = mm->brk + 0x02000000;
	return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
}
Commit	Line	Data
c767a54b JP	1	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
c767a54b JP	2
61c4628b SS	3	#include <linux/errno.h>
	4	#include <linux/kernel.h>
	5	#include <linux/mm.h>
	6	#include <linux/smp.h>
389d1fb1	7	#include <linux/prctl.h>
61c4628b SS	8	#include <linux/slab.h>
61c4628b SS	9	#include <linux/sched.h>
7f424a8b PZ	10	#include <linux/module.h>
7f424a8b PZ	11	#include <linux/pm.h>
aa276e1c	12	#include <linux/clockchips.h>
9d62dcdf	13	#include <linux/random.h>
7c68af6e	14	#include <linux/user-return-notifier.h>
814e2c84 AI	15	#include <linux/dmi.h>
814e2c84 AI	16	#include <linux/utsname.h>
90e24014 RW	17	#include <linux/stackprotector.h>
	18	#include <linux/tick.h>
	19	#include <linux/cpuidle.h>
61613521	20	#include <trace/events/power.h>
24f1e32c	21	#include <linux/hw_breakpoint.h>
93789b32	22	#include <asm/cpu.h>
d3ec5cae	23	#include <asm/apic.h>
2c1b284e	24	#include <asm/syscalls.h>
389d1fb1 JF	25	#include <asm/idle.h>
	26	#include <asm/uaccess.h>
	27	#include <asm/i387.h>
1361b83a	28	#include <asm/fpu-internal.h>
66cb5917	29	#include <asm/debugreg.h>
90e24014 RW	30	#include <asm/nmi.h>
90e24014 RW	31
45046892 TG	32	/*
	33	* per-CPU TSS segments. Threads are completely 'soft' on Linux,
	34	* no more per-task TSS's. The TSS size is kept cacheline-aligned
	35	* so they are allowed to end up in the .data..cacheline_aligned
	36	* section. Since TSS's are completely CPU-local, we want them
	37	* on exact cacheline boundaries, to eliminate cacheline ping-pong.
	38	*/
277d5b40	39	__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;
45046892	40
90e24014 RW	41	#ifdef CONFIG_X86_64
	42	static DEFINE_PER_CPU(unsigned char, is_idle);
	43	static ATOMIC_NOTIFIER_HEAD(idle_notifier);
	44
	45	void idle_notifier_register(struct notifier_block *n)
	46	{
	47	atomic_notifier_chain_register(&idle_notifier, n);
	48	}
	49	EXPORT_SYMBOL_GPL(idle_notifier_register);
	50
	51	void idle_notifier_unregister(struct notifier_block *n)
	52	{
	53	atomic_notifier_chain_unregister(&idle_notifier, n);
	54	}
	55	EXPORT_SYMBOL_GPL(idle_notifier_unregister);
	56	#endif
c1e3b377	57
aa283f49	58	struct kmem_cache *task_xstate_cachep;
5ee481da	59	EXPORT_SYMBOL_GPL(task_xstate_cachep);
61c4628b	60
55ccf3fe SS	61	/*
	62	* this gets called so that we can store lazy state into memory and copy the
	63	* current task into the new thread.
	64	*/
61c4628b SS	65	int arch_dup_task_struct(struct task_struct dst, struct task_struct src)
61c4628b SS	66	{
86603283 AK	67	int ret;
86603283 AK	68
61c4628b	69	dst = src;
86603283 AK	70	if (fpu_allocated(&src->thread.fpu)) {
	71	memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
	72	ret = fpu_alloc(&dst->thread.fpu);
	73	if (ret)
	74	return ret;
304bceda	75	fpu_copy(dst, src);
aa283f49	76	}
61c4628b SS	77	return 0;
	78	}
	79
aa283f49	80	void free_thread_xstate(struct task_struct *tsk)
61c4628b	81	{
86603283	82	fpu_free(&tsk->thread.fpu);
aa283f49 SS	83	}
aa283f49 SS	84
38e7c572	85	void arch_release_task_struct(struct task_struct *tsk)
aa283f49	86	{
38e7c572	87	free_thread_xstate(tsk);
61c4628b SS	88	}
	89
	90	void arch_task_cache_init(void)
	91	{
	92	task_xstate_cachep =
	93	kmem_cache_create("task_xstate", xstate_size,
	94	__alignof__(union thread_xstate),
2dff4405	95	SLAB_PANIC \| SLAB_NOTRACK, NULL);
7496d645	96	setup_xstate_comp();
61c4628b	97	}
7f424a8b	98
389d1fb1 JF	99	/*
	100	* Free current thread data structures etc..
	101	*/
	102	void exit_thread(void)
	103	{
	104	struct task_struct *me = current;
	105	struct thread_struct *t = &me->thread;
250981e6	106	unsigned long *bp = t->io_bitmap_ptr;
389d1fb1	107
250981e6	108	if (bp) {
389d1fb1 JF	109	struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
389d1fb1 JF	110
389d1fb1 JF	111	t->io_bitmap_ptr = NULL;
	112	clear_thread_flag(TIF_IO_BITMAP);
	113	/*
	114	* Careful, clear this in the TSS too:
	115	*/
	116	memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
	117	t->io_bitmap_max = 0;
	118	put_cpu();
250981e6	119	kfree(bp);
389d1fb1	120	}
1dcc8d7b SS	121
1dcc8d7b SS	122	drop_fpu(me);
389d1fb1 JF	123	}
	124
	125	void flush_thread(void)
	126	{
	127	struct task_struct *tsk = current;
	128
24f1e32c	129	flush_ptrace_hw_breakpoint(tsk);
389d1fb1	130	memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
304bceda SS	131	drop_init_fpu(tsk);
	132	/*
	133	* Free the FPU state for non xsave platforms. They get reallocated
	134	* lazily at the first use.
	135	*/
5d2bd700	136	if (!use_eager_fpu())
304bceda	137	free_thread_xstate(tsk);
389d1fb1 JF	138	}
	139
	140	static void hard_disable_TSC(void)
	141	{
	142	write_cr4(read_cr4() \| X86_CR4_TSD);
	143	}
	144
	145	void disable_TSC(void)
	146	{
	147	preempt_disable();
	148	if (!test_and_set_thread_flag(TIF_NOTSC))
	149	/*
	150	* Must flip the CPU state synchronously with
	151	* TIF_NOTSC in the current running context.
	152	*/
	153	hard_disable_TSC();
	154	preempt_enable();
	155	}
	156
	157	static void hard_enable_TSC(void)
	158	{
	159	write_cr4(read_cr4() & ~X86_CR4_TSD);
	160	}
	161
	162	static void enable_TSC(void)
	163	{
	164	preempt_disable();
	165	if (test_and_clear_thread_flag(TIF_NOTSC))
	166	/*
	167	* Must flip the CPU state synchronously with
	168	* TIF_NOTSC in the current running context.
	169	*/
	170	hard_enable_TSC();
	171	preempt_enable();
	172	}
	173
	174	int get_tsc_mode(unsigned long adr)
	175	{
	176	unsigned int val;
	177
	178	if (test_thread_flag(TIF_NOTSC))
	179	val = PR_TSC_SIGSEGV;
	180	else
	181	val = PR_TSC_ENABLE;
	182
	183	return put_user(val, (unsigned int __user *)adr);
	184	}
	185
	186	int set_tsc_mode(unsigned int val)
	187	{
	188	if (val == PR_TSC_SIGSEGV)
	189	disable_TSC();
	190	else if (val == PR_TSC_ENABLE)
	191	enable_TSC();
	192	else
	193	return -EINVAL;
	194
	195	return 0;
	196	}
	197
	198	void __switch_to_xtra(struct task_struct prev_p, struct task_struct next_p,
	199	struct tss_struct *tss)
	200	{
	201	struct thread_struct prev, next;
202
203	prev = &prev_p->thread;
204	next = &next_p->thread;
205
ea8e61b7 PZ	206	if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
	207	test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
	208	unsigned long debugctl = get_debugctlmsr();
	209
	210	debugctl &= ~DEBUGCTLMSR_BTF;
	211	if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
	212	debugctl \|= DEBUGCTLMSR_BTF;
	213
	214	update_debugctlmsr(debugctl);
	215	}
389d1fb1	216
389d1fb1 JF	217	if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
	218	test_tsk_thread_flag(next_p, TIF_NOTSC)) {
	219	/* prev and next are different */
	220	if (test_tsk_thread_flag(next_p, TIF_NOTSC))
	221	hard_disable_TSC();
	222	else
	223	hard_enable_TSC();
	224	}
	225
	226	if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
	227	/*
	228	* Copy the relevant range of the IO bitmap.
	229	* Normally this is 128 bytes or less:
	230	*/
	231	memcpy(tss->io_bitmap, next->io_bitmap_ptr,
	232	max(prev->io_bitmap_max, next->io_bitmap_max));
	233	} else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
	234	/*
	235	* Clear any possible leftover bits:
	236	*/
	237	memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
	238	}
7c68af6e	239	propagate_user_return_notify(prev_p, next_p);
389d1fb1 JF	240	}
389d1fb1 JF	241
00dba564 TG	242	/*
	243	* Idle related variables and functions
	244	*/
d1896049	245	unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
00dba564 TG	246	EXPORT_SYMBOL(boot_option_idle_override);
00dba564 TG	247
a476bda3	248	static void (*x86_idle)(void);
00dba564	249
90e24014 RW	250	#ifndef CONFIG_SMP
	251	static inline void play_dead(void)
	252	{
	253	BUG();
	254	}
	255	#endif
	256
	257	#ifdef CONFIG_X86_64
	258	void enter_idle(void)
	259	{
c6ae41e7	260	this_cpu_write(is_idle, 1);
90e24014 RW	261	atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
	262	}
	263
	264	static void __exit_idle(void)
	265	{
	266	if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
	267	return;
	268	atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
	269	}
	270
	271	/* Called from interrupts to signify idle end */
	272	void exit_idle(void)
	273	{
	274	/* idle loop has pid 0 */
	275	if (current->pid)
	276	return;
	277	__exit_idle();
	278	}
	279	#endif
	280
7d1a9417 TG	281	void arch_cpu_idle_enter(void)
	282	{
	283	local_touch_nmi();
	284	enter_idle();
	285	}
90e24014	286
7d1a9417 TG	287	void arch_cpu_idle_exit(void)
	288	{
	289	__exit_idle();
	290	}
90e24014	291
7d1a9417 TG	292	void arch_cpu_idle_dead(void)
	293	{
	294	play_dead();
	295	}
90e24014	296
7d1a9417 TG	297	/*
	298	* Called from the generic idle code.
	299	*/
	300	void arch_cpu_idle(void)
	301	{
16f8b05a	302	x86_idle();
90e24014 RW	303	}
90e24014 RW	304
00dba564	305	/*
7d1a9417	306	* We use this if we don't have any better idle routine..
00dba564 TG	307	*/
	308	void default_idle(void)
	309	{
4d0e42cc	310	trace_cpu_idle_rcuidle(1, smp_processor_id());
7d1a9417	311	safe_halt();
4d0e42cc	312	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
00dba564	313	}
60b8b1de	314	#ifdef CONFIG_APM_MODULE
00dba564 TG	315	EXPORT_SYMBOL(default_idle);
	316	#endif
	317
6a377ddc LB	318	#ifdef CONFIG_XEN
6a377ddc LB	319	bool xen_set_default_idle(void)
e5fd47bf	320	{
a476bda3	321	bool ret = !!x86_idle;
e5fd47bf	322
a476bda3	323	x86_idle = default_idle;
e5fd47bf KRW	324
	325	return ret;
	326	}
6a377ddc	327	#endif
d3ec5cae IV	328	void stop_this_cpu(void *dummy)
	329	{
	330	local_irq_disable();
	331	/*
	332	* Remove this CPU:
	333	*/
4f062896	334	set_cpu_online(smp_processor_id(), false);
d3ec5cae IV	335	disable_local_APIC();
d3ec5cae IV	336
27be4570 LB	337	for (;;)
27be4570 LB	338	halt();
7f424a8b PZ	339	}
7f424a8b PZ	340
02c68a02 LB	341	bool amd_e400_c1e_detected;
02c68a02 LB	342	EXPORT_SYMBOL(amd_e400_c1e_detected);
aa276e1c	343
02c68a02	344	static cpumask_var_t amd_e400_c1e_mask;
4faac97d	345
02c68a02	346	void amd_e400_remove_cpu(int cpu)
4faac97d	347	{
02c68a02 LB	348	if (amd_e400_c1e_mask != NULL)
02c68a02 LB	349	cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
4faac97d TG	350	}
4faac97d TG	351
aa276e1c	352	/*
02c68a02	353	* AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
aa276e1c TG	354	* pending message MSR. If we detect C1E, then we handle it the same
	355	* way as C3 power states (local apic timer and TSC stop)
	356	*/
02c68a02	357	static void amd_e400_idle(void)
aa276e1c	358	{
02c68a02	359	if (!amd_e400_c1e_detected) {
aa276e1c TG	360	u32 lo, hi;
	361
	362	rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
e8c534ec	363
aa276e1c	364	if (lo & K8_INTP_C1E_ACTIVE_MASK) {
02c68a02	365	amd_e400_c1e_detected = true;
40fb1715	366	if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
09bfeea1	367	mark_tsc_unstable("TSC halt in AMD C1E");
c767a54b	368	pr_info("System has AMD C1E enabled\n");
aa276e1c TG	369	}
	370	}
	371
02c68a02	372	if (amd_e400_c1e_detected) {
aa276e1c TG	373	int cpu = smp_processor_id();
aa276e1c TG	374
02c68a02 LB	375	if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
02c68a02 LB	376	cpumask_set_cpu(cpu, amd_e400_c1e_mask);
0beefa20	377	/*
f833bab8	378	* Force broadcast so ACPI can not interfere.
0beefa20	379	*/
aa276e1c TG	380	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
aa276e1c TG	381	&cpu);
c767a54b	382	pr_info("Switch to broadcast mode on CPU%d\n", cpu);
aa276e1c TG	383	}
aa276e1c TG	384	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
0beefa20	385
aa276e1c	386	default_idle();
0beefa20 TG	387
	388	/*
	389	* The switch back from broadcast mode needs to be
	390	* called with interrupts disabled.
	391	*/
ea811747 PZ	392	local_irq_disable();
	393	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
	394	local_irq_enable();
aa276e1c TG	395	} else
	396	default_idle();
	397	}
	398
148f9bb8	399	void select_idle_routine(const struct cpuinfo_x86 *c)
7f424a8b	400	{
3e5095d1	401	#ifdef CONFIG_SMP
7d1a9417	402	if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
c767a54b	403	pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
7f424a8b	404	#endif
7d1a9417	405	if (x86_idle \|\| boot_option_idle_override == IDLE_POLL)
6ddd2a27 TG	406	return;
6ddd2a27 TG	407
7d7dc116	408	if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
9d8888c2	409	/* E400: APIC timer interrupt does not wake up CPU from C1e */
c767a54b	410	pr_info("using AMD E400 aware idle routine\n");
a476bda3	411	x86_idle = amd_e400_idle;
6ddd2a27	412	} else
a476bda3	413	x86_idle = default_idle;
7f424a8b PZ	414	}
7f424a8b PZ	415
02c68a02	416	void __init init_amd_e400_c1e_mask(void)
30e1e6d1	417	{
02c68a02	418	/* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
a476bda3	419	if (x86_idle == amd_e400_idle)
02c68a02	420	zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
30e1e6d1 RR	421	}
30e1e6d1 RR	422
7f424a8b PZ	423	static int __init idle_setup(char *str)
7f424a8b PZ	424	{
ab6bc3e3 CG	425	if (!str)
	426	return -EINVAL;
	427
7f424a8b	428	if (!strcmp(str, "poll")) {
c767a54b	429	pr_info("using polling idle threads\n");
d1896049	430	boot_option_idle_override = IDLE_POLL;
7d1a9417	431	cpu_idle_poll_ctrl(true);
d1896049	432	} else if (!strcmp(str, "halt")) {
c1e3b377 ZY	433	/*
	434	* When the boot option of idle=halt is added, halt is
	435	* forced to be used for CPU idle. In such case CPU C2/C3
	436	* won't be used again.
	437	* To continue to load the CPU idle driver, don't touch
	438	* the boot_option_idle_override.
	439	*/
a476bda3	440	x86_idle = default_idle;
d1896049	441	boot_option_idle_override = IDLE_HALT;
da5e09a1 ZY	442	} else if (!strcmp(str, "nomwait")) {
	443	/*
	444	* If the boot option of "idle=nomwait" is added,
	445	* it means that mwait will be disabled for CPU C2/C3
	446	* states. In such case it won't touch the variable
	447	* of boot_option_idle_override.
	448	*/
d1896049	449	boot_option_idle_override = IDLE_NOMWAIT;
c1e3b377	450	} else
7f424a8b PZ	451	return -1;
7f424a8b PZ	452
7f424a8b PZ	453	return 0;
	454	}
	455	early_param("idle", idle_setup);
	456
9d62dcdf AW	457	unsigned long arch_align_stack(unsigned long sp)
	458	{
	459	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
	460	sp -= get_random_int() % 8192;
	461	return sp & ~0xf;
	462	}
	463
	464	unsigned long arch_randomize_brk(struct mm_struct *mm)
	465	{
	466	unsigned long range_end = mm->brk + 0x02000000;
	467	return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
	468	}
	469