[linux-2.6-block.git] / arch / x86 / kernel / process.c

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/prctl.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/clockchips.h>
#include <linux/random.h>
#include <linux/user-return-notifier.h>
#include <linux/dmi.h>
#include <linux/utsname.h>
#include <linux/stackprotector.h>
#include <linux/tick.h>
#include <linux/cpuidle.h>
#include <trace/events/power.h>
#include <linux/hw_breakpoint.h>
#include <asm/cpu.h>
#include <asm/apic.h>
#include <asm/syscalls.h>
#include <asm/idle.h>
#include <asm/uaccess.h>
#include <asm/i387.h>
#include <asm/fpu-internal.h>
#include <asm/debugreg.h>
#include <asm/nmi.h>
#include <asm/tlbflush.h>

/*
 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
 * no more per-task TSS's. The TSS size is kept cacheline-aligned
 * so they are allowed to end up in the .data..cacheline_aligned
 * section. Since TSS's are completely CPU-local, we want them
 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
 */
__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = INIT_TSS;
EXPORT_PER_CPU_SYMBOL_GPL(cpu_tss);

#ifdef CONFIG_X86_64
static DEFINE_PER_CPU(unsigned char, is_idle);
static ATOMIC_NOTIFIER_HEAD(idle_notifier);

void idle_notifier_register(struct notifier_block *n)
{
	atomic_notifier_chain_register(&idle_notifier, n);
}
EXPORT_SYMBOL_GPL(idle_notifier_register);

void idle_notifier_unregister(struct notifier_block *n)
{
	atomic_notifier_chain_unregister(&idle_notifier, n);
}
EXPORT_SYMBOL_GPL(idle_notifier_unregister);
#endif

struct kmem_cache *task_xstate_cachep;
EXPORT_SYMBOL_GPL(task_xstate_cachep);

/*
 * this gets called so that we can store lazy state into memory and copy the
 * current task into the new thread.
 */
int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
{
	*dst = *src;

	dst->thread.fpu_counter = 0;
	dst->thread.fpu.has_fpu = 0;
	dst->thread.fpu.last_cpu = ~0;
	dst->thread.fpu.state = NULL;
	if (tsk_used_math(src)) {
		int err = fpu_alloc(&dst->thread.fpu);
		if (err)
			return err;
		fpu_copy(dst, src);
	}
	return 0;
}

void free_thread_xstate(struct task_struct *tsk)
{
	fpu_free(&tsk->thread.fpu);
}

void arch_release_task_struct(struct task_struct *tsk)
{
	free_thread_xstate(tsk);
}

void arch_task_cache_init(void)
{
        task_xstate_cachep =
        	kmem_cache_create("task_xstate", xstate_size,
				  __alignof__(union thread_xstate),
				  SLAB_PANIC | SLAB_NOTRACK, NULL);
	setup_xstate_comp();
}

/*
 * Free current thread data structures etc..
 */
void exit_thread(void)
{
	struct task_struct *me = current;
	struct thread_struct *t = &me->thread;
	unsigned long *bp = t->io_bitmap_ptr;

	if (bp) {
		struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu());

		t->io_bitmap_ptr = NULL;
		clear_thread_flag(TIF_IO_BITMAP);
		/*
		 * Careful, clear this in the TSS too:
		 */
		memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
		t->io_bitmap_max = 0;
		put_cpu();
		kfree(bp);
	}

	drop_fpu(me);
}

void flush_thread(void)
{
	struct task_struct *tsk = current;

	flush_ptrace_hw_breakpoint(tsk);
	memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
	drop_init_fpu(tsk);
	/*
	 * Free the FPU state for non xsave platforms. They get reallocated
	 * lazily at the first use.
	 */
	if (!use_eager_fpu())
		free_thread_xstate(tsk);
}

static void hard_disable_TSC(void)
{
	cr4_set_bits(X86_CR4_TSD);
}

void disable_TSC(void)
{
	preempt_disable();
	if (!test_and_set_thread_flag(TIF_NOTSC))
		/*
		 * Must flip the CPU state synchronously with
		 * TIF_NOTSC in the current running context.
		 */
		hard_disable_TSC();
	preempt_enable();
}

static void hard_enable_TSC(void)
{
	cr4_clear_bits(X86_CR4_TSD);
}

static void enable_TSC(void)
{
	preempt_disable();
	if (test_and_clear_thread_flag(TIF_NOTSC))
		/*
		 * Must flip the CPU state synchronously with
		 * TIF_NOTSC in the current running context.
		 */
		hard_enable_TSC();
	preempt_enable();
}

int get_tsc_mode(unsigned long adr)
{
	unsigned int val;

	if (test_thread_flag(TIF_NOTSC))
		val = PR_TSC_SIGSEGV;
	else
		val = PR_TSC_ENABLE;

	return put_user(val, (unsigned int __user *)adr);
}

int set_tsc_mode(unsigned int val)
{
	if (val == PR_TSC_SIGSEGV)
		disable_TSC();
	else if (val == PR_TSC_ENABLE)
		enable_TSC();
	else
		return -EINVAL;

	return 0;
}

void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
		      struct tss_struct *tss)
{
	struct thread_struct *prev, *next;

	prev = &prev_p->thread;
	next = &next_p->thread;

	if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
	    test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
		unsigned long debugctl = get_debugctlmsr();

		debugctl &= ~DEBUGCTLMSR_BTF;
		if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
			debugctl |= DEBUGCTLMSR_BTF;

		update_debugctlmsr(debugctl);
	}

	if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
	    test_tsk_thread_flag(next_p, TIF_NOTSC)) {
		/* prev and next are different */
		if (test_tsk_thread_flag(next_p, TIF_NOTSC))
			hard_disable_TSC();
		else
			hard_enable_TSC();
	}

	if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
		/*
		 * Copy the relevant range of the IO bitmap.
		 * Normally this is 128 bytes or less:
		 */
		memcpy(tss->io_bitmap, next->io_bitmap_ptr,
		       max(prev->io_bitmap_max, next->io_bitmap_max));
	} else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
		/*
		 * Clear any possible leftover bits:
		 */
		memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
	}
	propagate_user_return_notify(prev_p, next_p);
}

/*
 * Idle related variables and functions
 */
unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
EXPORT_SYMBOL(boot_option_idle_override);

static void (*x86_idle)(void);

#ifndef CONFIG_SMP
static inline void play_dead(void)
{
	BUG();
}
#endif

#ifdef CONFIG_X86_64
void enter_idle(void)
{
	this_cpu_write(is_idle, 1);
	atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
}

static void __exit_idle(void)
{
	if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
		return;
	atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
}

/* Called from interrupts to signify idle end */
void exit_idle(void)
{
	/* idle loop has pid 0 */
	if (current->pid)
		return;
	__exit_idle();
}
#endif

void arch_cpu_idle_enter(void)
{
	local_touch_nmi();
	enter_idle();
}

void arch_cpu_idle_exit(void)
{
	__exit_idle();
}

void arch_cpu_idle_dead(void)
{
	play_dead();
}

/*
 * Called from the generic idle code.
 */
void arch_cpu_idle(void)
{
	x86_idle();
}

/*
 * We use this if we don't have any better idle routine..
 */
void default_idle(void)
{
	trace_cpu_idle_rcuidle(1, smp_processor_id());
	safe_halt();
	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
}
#ifdef CONFIG_APM_MODULE
EXPORT_SYMBOL(default_idle);
#endif

#ifdef CONFIG_XEN
bool xen_set_default_idle(void)
{
	bool ret = !!x86_idle;

	x86_idle = default_idle;

	return ret;
}
#endif
void stop_this_cpu(void *dummy)
{
	local_irq_disable();
	/*
	 * Remove this CPU:
	 */
	set_cpu_online(smp_processor_id(), false);
	disable_local_APIC();

	for (;;)
		halt();
}

bool amd_e400_c1e_detected;
EXPORT_SYMBOL(amd_e400_c1e_detected);

static cpumask_var_t amd_e400_c1e_mask;

void amd_e400_remove_cpu(int cpu)
{
	if (amd_e400_c1e_mask != NULL)
		cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
}

/*
 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
 * pending message MSR. If we detect C1E, then we handle it the same
 * way as C3 power states (local apic timer and TSC stop)
 */
static void amd_e400_idle(void)
{
	if (!amd_e400_c1e_detected) {
		u32 lo, hi;

		rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);

		if (lo & K8_INTP_C1E_ACTIVE_MASK) {
			amd_e400_c1e_detected = true;
			if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
				mark_tsc_unstable("TSC halt in AMD C1E");
			pr_info("System has AMD C1E enabled\n");
		}
	}

	if (amd_e400_c1e_detected) {
		int cpu = smp_processor_id();

		if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
			cpumask_set_cpu(cpu, amd_e400_c1e_mask);
			/*
			 * Force broadcast so ACPI can not interfere.
			 */
			clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
					   &cpu);
			pr_info("Switch to broadcast mode on CPU%d\n", cpu);
		}
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);

		default_idle();

		/*
		 * The switch back from broadcast mode needs to be
		 * called with interrupts disabled.
		 */
		local_irq_disable();
		clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
		local_irq_enable();
	} else
		default_idle();
}

void select_idle_routine(const struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
	if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
		pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
#endif
	if (x86_idle || boot_option_idle_override == IDLE_POLL)
		return;

	if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
		/* E400: APIC timer interrupt does not wake up CPU from C1e */
		pr_info("using AMD E400 aware idle routine\n");
		x86_idle = amd_e400_idle;
	} else
		x86_idle = default_idle;
}

void __init init_amd_e400_c1e_mask(void)
{
	/* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
	if (x86_idle == amd_e400_idle)
		zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
}

static int __init idle_setup(char *str)
{
	if (!str)
		return -EINVAL;

	if (!strcmp(str, "poll")) {
		pr_info("using polling idle threads\n");
		boot_option_idle_override = IDLE_POLL;
		cpu_idle_poll_ctrl(true);
	} else if (!strcmp(str, "halt")) {
		/*
		 * When the boot option of idle=halt is added, halt is
		 * forced to be used for CPU idle. In such case CPU C2/C3
		 * won't be used again.
		 * To continue to load the CPU idle driver, don't touch
		 * the boot_option_idle_override.
		 */
		x86_idle = default_idle;
		boot_option_idle_override = IDLE_HALT;
	} else if (!strcmp(str, "nomwait")) {
		/*
		 * If the boot option of "idle=nomwait" is added,
		 * it means that mwait will be disabled for CPU C2/C3
		 * states. In such case it won't touch the variable
		 * of boot_option_idle_override.
		 */
		boot_option_idle_override = IDLE_NOMWAIT;
	} else
		return -1;

	return 0;
}
early_param("idle", idle_setup);

unsigned long arch_align_stack(unsigned long sp)
{
	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
		sp -= get_random_int() % 8192;
	return sp & ~0xf;
}

unsigned long arch_randomize_brk(struct mm_struct *mm)
{
	unsigned long range_end = mm->brk + 0x02000000;
	return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
}
Commit	Line	Data
c767a54b JP	1	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
c767a54b JP	2
61c4628b SS	3	#include <linux/errno.h>
	4	#include <linux/kernel.h>
	5	#include <linux/mm.h>
	6	#include <linux/smp.h>
389d1fb1	7	#include <linux/prctl.h>
61c4628b SS	8	#include <linux/slab.h>
61c4628b SS	9	#include <linux/sched.h>
7f424a8b PZ	10	#include <linux/module.h>
7f424a8b PZ	11	#include <linux/pm.h>
aa276e1c	12	#include <linux/clockchips.h>
9d62dcdf	13	#include <linux/random.h>
7c68af6e	14	#include <linux/user-return-notifier.h>
814e2c84 AI	15	#include <linux/dmi.h>
814e2c84 AI	16	#include <linux/utsname.h>
90e24014 RW	17	#include <linux/stackprotector.h>
	18	#include <linux/tick.h>
	19	#include <linux/cpuidle.h>
61613521	20	#include <trace/events/power.h>
24f1e32c	21	#include <linux/hw_breakpoint.h>
93789b32	22	#include <asm/cpu.h>
d3ec5cae	23	#include <asm/apic.h>
2c1b284e	24	#include <asm/syscalls.h>
389d1fb1 JF	25	#include <asm/idle.h>
	26	#include <asm/uaccess.h>
	27	#include <asm/i387.h>
1361b83a	28	#include <asm/fpu-internal.h>
66cb5917	29	#include <asm/debugreg.h>
90e24014	30	#include <asm/nmi.h>
375074cc	31	#include <asm/tlbflush.h>
90e24014	32
45046892 TG	33	/*
	34	* per-CPU TSS segments. Threads are completely 'soft' on Linux,
	35	* no more per-task TSS's. The TSS size is kept cacheline-aligned
	36	* so they are allowed to end up in the .data..cacheline_aligned
	37	* section. Since TSS's are completely CPU-local, we want them
	38	* on exact cacheline boundaries, to eliminate cacheline ping-pong.
	39	*/
24933b82 AL	40	__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = INIT_TSS;
24933b82 AL	41	EXPORT_PER_CPU_SYMBOL_GPL(cpu_tss);
45046892	42
90e24014 RW	43	#ifdef CONFIG_X86_64
	44	static DEFINE_PER_CPU(unsigned char, is_idle);
	45	static ATOMIC_NOTIFIER_HEAD(idle_notifier);
	46
	47	void idle_notifier_register(struct notifier_block *n)
	48	{
	49	atomic_notifier_chain_register(&idle_notifier, n);
	50	}
	51	EXPORT_SYMBOL_GPL(idle_notifier_register);
	52
	53	void idle_notifier_unregister(struct notifier_block *n)
	54	{
	55	atomic_notifier_chain_unregister(&idle_notifier, n);
	56	}
	57	EXPORT_SYMBOL_GPL(idle_notifier_unregister);
	58	#endif
c1e3b377	59
aa283f49	60	struct kmem_cache *task_xstate_cachep;
5ee481da	61	EXPORT_SYMBOL_GPL(task_xstate_cachep);
61c4628b	62
55ccf3fe SS	63	/*
	64	* this gets called so that we can store lazy state into memory and copy the
	65	* current task into the new thread.
	66	*/
61c4628b SS	67	int arch_dup_task_struct(struct task_struct dst, struct task_struct src)
	68	{
	69	dst = src;
f1853505	70
dc56c0f9	71	dst->thread.fpu_counter = 0;
5e23fee2 ON	72	dst->thread.fpu.has_fpu = 0;
	73	dst->thread.fpu.last_cpu = ~0;
	74	dst->thread.fpu.state = NULL;
f1853505 ON	75	if (tsk_used_math(src)) {
	76	int err = fpu_alloc(&dst->thread.fpu);
	77	if (err)
	78	return err;
304bceda	79	fpu_copy(dst, src);
aa283f49	80	}
61c4628b SS	81	return 0;
	82	}
	83
aa283f49	84	void free_thread_xstate(struct task_struct *tsk)
61c4628b	85	{
86603283	86	fpu_free(&tsk->thread.fpu);
aa283f49 SS	87	}
aa283f49 SS	88
38e7c572	89	void arch_release_task_struct(struct task_struct *tsk)
aa283f49	90	{
38e7c572	91	free_thread_xstate(tsk);
61c4628b SS	92	}
	93
	94	void arch_task_cache_init(void)
	95	{
	96	task_xstate_cachep =
	97	kmem_cache_create("task_xstate", xstate_size,
	98	__alignof__(union thread_xstate),
2dff4405	99	SLAB_PANIC \| SLAB_NOTRACK, NULL);
7496d645	100	setup_xstate_comp();
61c4628b	101	}
7f424a8b	102
389d1fb1 JF	103	/*
	104	* Free current thread data structures etc..
	105	*/
	106	void exit_thread(void)
	107	{
	108	struct task_struct *me = current;
	109	struct thread_struct *t = &me->thread;
250981e6	110	unsigned long *bp = t->io_bitmap_ptr;
389d1fb1	111
250981e6	112	if (bp) {
24933b82	113	struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu());
389d1fb1	114
389d1fb1 JF	115	t->io_bitmap_ptr = NULL;
	116	clear_thread_flag(TIF_IO_BITMAP);
	117	/*
	118	* Careful, clear this in the TSS too:
	119	*/
	120	memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
	121	t->io_bitmap_max = 0;
	122	put_cpu();
250981e6	123	kfree(bp);
389d1fb1	124	}
1dcc8d7b SS	125
1dcc8d7b SS	126	drop_fpu(me);
389d1fb1 JF	127	}
	128
	129	void flush_thread(void)
	130	{
	131	struct task_struct *tsk = current;
	132
24f1e32c	133	flush_ptrace_hw_breakpoint(tsk);
389d1fb1	134	memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
304bceda SS	135	drop_init_fpu(tsk);
	136	/*
	137	* Free the FPU state for non xsave platforms. They get reallocated
	138	* lazily at the first use.
	139	*/
5d2bd700	140	if (!use_eager_fpu())
304bceda	141	free_thread_xstate(tsk);
389d1fb1 JF	142	}
	143
	144	static void hard_disable_TSC(void)
	145	{
375074cc	146	cr4_set_bits(X86_CR4_TSD);
389d1fb1 JF	147	}
	148
	149	void disable_TSC(void)
	150	{
	151	preempt_disable();
	152	if (!test_and_set_thread_flag(TIF_NOTSC))
	153	/*
	154	* Must flip the CPU state synchronously with
	155	* TIF_NOTSC in the current running context.
	156	*/
	157	hard_disable_TSC();
	158	preempt_enable();
	159	}
	160
	161	static void hard_enable_TSC(void)
	162	{
375074cc	163	cr4_clear_bits(X86_CR4_TSD);
389d1fb1 JF	164	}
	165
	166	static void enable_TSC(void)
	167	{
	168	preempt_disable();
	169	if (test_and_clear_thread_flag(TIF_NOTSC))
	170	/*
	171	* Must flip the CPU state synchronously with
	172	* TIF_NOTSC in the current running context.
	173	*/
	174	hard_enable_TSC();
	175	preempt_enable();
	176	}
	177
	178	int get_tsc_mode(unsigned long adr)
	179	{
	180	unsigned int val;
	181
	182	if (test_thread_flag(TIF_NOTSC))
	183	val = PR_TSC_SIGSEGV;
	184	else
	185	val = PR_TSC_ENABLE;
	186
	187	return put_user(val, (unsigned int __user *)adr);
	188	}
	189
	190	int set_tsc_mode(unsigned int val)
	191	{
	192	if (val == PR_TSC_SIGSEGV)
	193	disable_TSC();
	194	else if (val == PR_TSC_ENABLE)
	195	enable_TSC();
	196	else
	197	return -EINVAL;
	198
	199	return 0;
	200	}
	201
	202	void __switch_to_xtra(struct task_struct prev_p, struct task_struct next_p,
	203	struct tss_struct *tss)
	204	{
	205	struct thread_struct prev, next;
	206
	207	prev = &prev_p->thread;
	208	next = &next_p->thread;
	209
ea8e61b7 PZ	210	if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
	211	test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
	212	unsigned long debugctl = get_debugctlmsr();
	213
	214	debugctl &= ~DEBUGCTLMSR_BTF;
	215	if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
	216	debugctl \|= DEBUGCTLMSR_BTF;
	217
	218	update_debugctlmsr(debugctl);
	219	}
389d1fb1	220
389d1fb1 JF	221	if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
	222	test_tsk_thread_flag(next_p, TIF_NOTSC)) {
	223	/* prev and next are different */
	224	if (test_tsk_thread_flag(next_p, TIF_NOTSC))
	225	hard_disable_TSC();
	226	else
	227	hard_enable_TSC();
	228	}
	229
	230	if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
	231	/*
	232	* Copy the relevant range of the IO bitmap.
	233	* Normally this is 128 bytes or less:
	234	*/
	235	memcpy(tss->io_bitmap, next->io_bitmap_ptr,
	236	max(prev->io_bitmap_max, next->io_bitmap_max));
	237	} else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
	238	/*
	239	* Clear any possible leftover bits:
	240	*/
	241	memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
	242	}
7c68af6e	243	propagate_user_return_notify(prev_p, next_p);
389d1fb1 JF	244	}
389d1fb1 JF	245
00dba564 TG	246	/*
	247	* Idle related variables and functions
	248	*/
d1896049	249	unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
00dba564 TG	250	EXPORT_SYMBOL(boot_option_idle_override);
00dba564 TG	251
a476bda3	252	static void (*x86_idle)(void);
00dba564	253
90e24014 RW	254	#ifndef CONFIG_SMP
	255	static inline void play_dead(void)
	256	{
	257	BUG();
	258	}
	259	#endif
	260
	261	#ifdef CONFIG_X86_64
	262	void enter_idle(void)
	263	{
c6ae41e7	264	this_cpu_write(is_idle, 1);
90e24014 RW	265	atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
	266	}
	267
	268	static void __exit_idle(void)
	269	{
	270	if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
	271	return;
	272	atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
	273	}
	274
	275	/* Called from interrupts to signify idle end */
	276	void exit_idle(void)
	277	{
	278	/* idle loop has pid 0 */
	279	if (current->pid)
	280	return;
	281	__exit_idle();
	282	}
	283	#endif
	284
7d1a9417 TG	285	void arch_cpu_idle_enter(void)
	286	{
	287	local_touch_nmi();
	288	enter_idle();
	289	}
90e24014	290
7d1a9417 TG	291	void arch_cpu_idle_exit(void)
	292	{
	293	__exit_idle();
	294	}
90e24014	295
7d1a9417 TG	296	void arch_cpu_idle_dead(void)
	297	{
	298	play_dead();
	299	}
90e24014	300
7d1a9417 TG	301	/*
	302	* Called from the generic idle code.
	303	*/
	304	void arch_cpu_idle(void)
	305	{
16f8b05a	306	x86_idle();
90e24014 RW	307	}
90e24014 RW	308
00dba564	309	/*
7d1a9417	310	* We use this if we don't have any better idle routine..
00dba564 TG	311	*/
	312	void default_idle(void)
	313	{
4d0e42cc	314	trace_cpu_idle_rcuidle(1, smp_processor_id());
7d1a9417	315	safe_halt();
4d0e42cc	316	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
00dba564	317	}
60b8b1de	318	#ifdef CONFIG_APM_MODULE
00dba564 TG	319	EXPORT_SYMBOL(default_idle);
	320	#endif
	321
6a377ddc LB	322	#ifdef CONFIG_XEN
6a377ddc LB	323	bool xen_set_default_idle(void)
e5fd47bf	324	{
a476bda3	325	bool ret = !!x86_idle;
e5fd47bf	326
a476bda3	327	x86_idle = default_idle;
e5fd47bf KRW	328
	329	return ret;
	330	}
6a377ddc	331	#endif
d3ec5cae IV	332	void stop_this_cpu(void *dummy)
	333	{
	334	local_irq_disable();
	335	/*
	336	* Remove this CPU:
	337	*/
4f062896	338	set_cpu_online(smp_processor_id(), false);
d3ec5cae IV	339	disable_local_APIC();
d3ec5cae IV	340
27be4570 LB	341	for (;;)
27be4570 LB	342	halt();
7f424a8b PZ	343	}
7f424a8b PZ	344
02c68a02 LB	345	bool amd_e400_c1e_detected;
02c68a02 LB	346	EXPORT_SYMBOL(amd_e400_c1e_detected);
aa276e1c	347
02c68a02	348	static cpumask_var_t amd_e400_c1e_mask;
4faac97d	349
02c68a02	350	void amd_e400_remove_cpu(int cpu)
4faac97d	351	{
02c68a02 LB	352	if (amd_e400_c1e_mask != NULL)
02c68a02 LB	353	cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
4faac97d TG	354	}
4faac97d TG	355
aa276e1c	356	/*
02c68a02	357	* AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
aa276e1c TG	358	* pending message MSR. If we detect C1E, then we handle it the same
	359	* way as C3 power states (local apic timer and TSC stop)
	360	*/
02c68a02	361	static void amd_e400_idle(void)
aa276e1c	362	{
02c68a02	363	if (!amd_e400_c1e_detected) {
aa276e1c TG	364	u32 lo, hi;
	365
	366	rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
e8c534ec	367
aa276e1c	368	if (lo & K8_INTP_C1E_ACTIVE_MASK) {
02c68a02	369	amd_e400_c1e_detected = true;
40fb1715	370	if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
09bfeea1	371	mark_tsc_unstable("TSC halt in AMD C1E");
c767a54b	372	pr_info("System has AMD C1E enabled\n");
aa276e1c TG	373	}
	374	}
	375
02c68a02	376	if (amd_e400_c1e_detected) {
aa276e1c TG	377	int cpu = smp_processor_id();
aa276e1c TG	378
02c68a02 LB	379	if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
02c68a02 LB	380	cpumask_set_cpu(cpu, amd_e400_c1e_mask);
0beefa20	381	/*
f833bab8	382	* Force broadcast so ACPI can not interfere.
0beefa20	383	*/
aa276e1c TG	384	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
aa276e1c TG	385	&cpu);
c767a54b	386	pr_info("Switch to broadcast mode on CPU%d\n", cpu);
aa276e1c TG	387	}
aa276e1c TG	388	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
0beefa20	389
aa276e1c	390	default_idle();
0beefa20 TG	391
	392	/*
	393	* The switch back from broadcast mode needs to be
	394	* called with interrupts disabled.
	395	*/
ea811747 PZ	396	local_irq_disable();
	397	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
	398	local_irq_enable();
aa276e1c TG	399	} else
	400	default_idle();
	401	}
	402
148f9bb8	403	void select_idle_routine(const struct cpuinfo_x86 *c)
7f424a8b	404	{
3e5095d1	405	#ifdef CONFIG_SMP
7d1a9417	406	if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
c767a54b	407	pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
7f424a8b	408	#endif
7d1a9417	409	if (x86_idle \|\| boot_option_idle_override == IDLE_POLL)
6ddd2a27 TG	410	return;
6ddd2a27 TG	411
7d7dc116	412	if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
9d8888c2	413	/* E400: APIC timer interrupt does not wake up CPU from C1e */
c767a54b	414	pr_info("using AMD E400 aware idle routine\n");
a476bda3	415	x86_idle = amd_e400_idle;
6ddd2a27	416	} else
a476bda3	417	x86_idle = default_idle;
7f424a8b PZ	418	}
7f424a8b PZ	419
02c68a02	420	void __init init_amd_e400_c1e_mask(void)
30e1e6d1	421	{
02c68a02	422	/* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
a476bda3	423	if (x86_idle == amd_e400_idle)
02c68a02	424	zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
30e1e6d1 RR	425	}
30e1e6d1 RR	426
7f424a8b PZ	427	static int __init idle_setup(char *str)
7f424a8b PZ	428	{
ab6bc3e3 CG	429	if (!str)
	430	return -EINVAL;
	431
7f424a8b	432	if (!strcmp(str, "poll")) {
c767a54b	433	pr_info("using polling idle threads\n");
d1896049	434	boot_option_idle_override = IDLE_POLL;
7d1a9417	435	cpu_idle_poll_ctrl(true);
d1896049	436	} else if (!strcmp(str, "halt")) {
c1e3b377 ZY	437	/*
	438	* When the boot option of idle=halt is added, halt is
	439	* forced to be used for CPU idle. In such case CPU C2/C3
	440	* won't be used again.
	441	* To continue to load the CPU idle driver, don't touch
	442	* the boot_option_idle_override.
	443	*/
a476bda3	444	x86_idle = default_idle;
d1896049	445	boot_option_idle_override = IDLE_HALT;
da5e09a1 ZY	446	} else if (!strcmp(str, "nomwait")) {
	447	/*
	448	* If the boot option of "idle=nomwait" is added,
	449	* it means that mwait will be disabled for CPU C2/C3
	450	* states. In such case it won't touch the variable
	451	* of boot_option_idle_override.
	452	*/
d1896049	453	boot_option_idle_override = IDLE_NOMWAIT;
c1e3b377	454	} else
7f424a8b PZ	455	return -1;
7f424a8b PZ	456
7f424a8b PZ	457	return 0;
	458	}
	459	early_param("idle", idle_setup);
	460
9d62dcdf AW	461	unsigned long arch_align_stack(unsigned long sp)
	462	{
	463	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
	464	sp -= get_random_int() % 8192;
	465	return sp & ~0xf;
	466	}
	467
	468	unsigned long arch_randomize_brk(struct mm_struct *mm)
	469	{
	470	unsigned long range_end = mm->brk + 0x02000000;
	471	return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
	472	}
	473