|author||Masanari Iida <firstname.lastname@example.org>||2015-07-06 23:41:57 +0900|
|committer||Jonathan Corbet <email@example.com>||2015-07-10 14:00:51 -0600|
Doc: powerpc: Fix typos in Documentation/powerpc
This patch fix some spelling typo found in Documentation/powerpc. Signed-off-by: Masanari Iida <firstname.lastname@example.org> Acked-by: Ian Munsie <email@example.com> Signed-off-by: Jonathan Corbet <firstname.lastname@example.org>
3 files changed, 5 insertions, 5 deletions
diff --git a/Documentation/powerpc/cxl.txt b/Documentation/powerpc/cxl.txt
index 2a230d01cd8c..205c1b81625c 100644
@@ -133,7 +133,7 @@ User API
The following file operations are supported on both slave and
- A userspace library libcxl is avaliable here:
+ A userspace library libcxl is available here:
This provides a C interface to this kernel API.
diff --git a/Documentation/powerpc/dscr.txt b/Documentation/powerpc/dscr.txt
index 1ff4400c57b3..ece300c64f76 100644
@@ -4,7 +4,7 @@
DSCR register in powerpc allows user to have some control of prefetch of data
stream in the processor. Please refer to the ISA documents or related manual
for more detailed information regarding how to use this DSCR to attain this
-control of the pefetches . This document here provides an overview of kernel
+control of the prefetches . This document here provides an overview of kernel
support for DSCR, related kernel objects, it's functionalities and exported
@@ -44,7 +44,7 @@ user interface.
value into every CPU's DSCR register right away and updates the current
thread's DSCR value as well.
- Changing the CPU specif DSCR default value in the sysfs does exactly
+ Changing the CPU specific DSCR default value in the sysfs does exactly
the same thing as above but unlike the global one above, it just changes
stuff for that particular CPU instead for all the CPUs on the system.
@@ -62,7 +62,7 @@ user interface.
Accessing DSCR through user level SPR (0x03) from user space will first
create a facility unavailable exception. Inside this exception handler
- all mfspr isntruction based read attempts will get emulated and returned
+ all mfspr instruction based read attempts will get emulated and returned
where as the first mtspr instruction based write attempts will enable
the DSCR facility for the next time around (both for read and write) by
setting DSCR facility in the FSCR register.
diff --git a/Documentation/powerpc/qe_firmware.txt b/Documentation/powerpc/qe_firmware.txt
index 2031ddb33d09..e7ac24aec4ff 100644
@@ -117,7 +117,7 @@ specific been defined. This table describes the structure.
This is a double word bit array (64 bits) that defines special functionality
-which has an impact on the softwarew drivers. Each bit has its own impact
+which has an impact on the software drivers. Each bit has its own impact
and has special instructions for the s/w associated with it. This structure is
described in this table: