1. Use Galois LFSR instead of Fibonacci LFSR.
2. Use XNOR gates instead of XOR gates.
3. Add tap sizes for LFSRs ranging from 3-bits to 15-bits.
4. Add spin parameter.
1. Fibonacci LFSRs have the following drawbacks:
a. Their next state can not be computed in one cycle, since the input
bit must be propagated serially through the XOR gates. Galois
LFSRs however, can be computed instantly with XOR-masks.
b. Their state changes cannot be considered "irregular", even by I/O
standards. Actually, if the current state of an n-bit LFSR is x,
then the next will either be (x >> 1) or (2^n + (x >> 1)). Galois
LFSRs have instead their XOR gates interleaved with their bits,
which means that the inner bits are changed as well, besides of
the shifting. If the number of taps is z, this means that the
different outcomes are 2^(z + 1).
2. An LFSR with XOR gates has the all-zeroes state as illegal. Since
zero is valid for most I/O operations, it would be more intuitive to
use XNOR gates, that have as the all-ones state as illegal.
3. Allow smaller I/O benchmarks to use LFSRs.
4. The spin parameter follows the same rationale as in 1b. To make the
LFSR outcome "appear" less predictable, we can spin internally the
LFSR state and produce the i-th number. To understand the spin
parameter, consider the following state sequence of a 3-bit LFSR:
0, 2, 3, 5, 6, 1, 4
Same LFSR, spin value 2: 0, 3, 6, 4, 2, 5, 1
But what is the benefit from using spin? Well, the benefits are
a. For the same I/O size, we can create a different I/O sequences.
b. Following the rationale of 1b, we can have more variable outcomes.
If the spin value is "i" and the taps are "z", the number of
different outcomes become i * 2^(z + 1).
Signed-off-by: Alex Pyrgiotis <email@example.com>
Signed-off-by: Jens Axboe <firstname.lastname@example.org>