RISC-V: fix sifive and thead section mismatches in errata
authorRandy Dunlap <rdunlap@infradead.org>
Sat, 29 Apr 2023 15:52:47 +0000 (08:52 -0700)
committerPalmer Dabbelt <palmer@rivosinc.com>
Sat, 29 Apr 2023 20:18:19 +0000 (13:18 -0700)
commita2a58b5ca124f4a0178d0ada801f1ed2c84c393d
treef719ece31c9051edd2b05a31f9432f4f8ea90ff8
parent41cad8284d5e6bf1d49d3c10a6b52ee1ae866a20
RISC-V: fix sifive and thead section mismatches in errata

When CONFIG_MODULES is set, __init_or_module becomes <empty>, but when
CONFIG_MODULES is not set, __init_or_module becomes __init.
In the latter case, it causes section mismatch warnings:

WARNING: modpost: vmlinux.o: section mismatch in reference: riscv_fill_cpu_mfr_info (section: .text) -> sifive_errata_patch_func (section: .init.text)
WARNING: modpost: vmlinux.o: section mismatch in reference: riscv_fill_cpu_mfr_info (section: .text) -> thead_errata_patch_func (section: .init.text)

Fixes: bb3f89487fd9 ("RISC-V: hwprobe: Remove __init on probe_vendor_features()")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reviewed-by: Evan Green <evan@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230429155247.12131-1-rdunlap@infradead.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/errata/sifive/errata.c
arch/riscv/errata/thead/errata.c