#define nop __asm__ __volatile__ ("nop": : :"memory")
-#if defined(__SH4A__)
-#define mb() __asm__ __volatile__ ("synco": : :"memory")
-#else
-#define mb() __asm__ __volatile__ (" " : : : "memory")
-#endif
+#define mb() \
+ do { \
+ if (arch_flags & ARCH_FLAG_1) \
+ __asm__ __volatile__ ("synco": : :"memory"); \
+ else \
+ __asm__ __volatile__ (" " : : : "memory"); \
+ } while (0)
#define read_barrier() mb()
#define write_barrier() mb()
+#define CPU_HAS_LLSC 0x0040
+
+static inline int arch_init(char *envp[])
+{
+ Elf32_auxv_t *auxv;
+
+ while (*envp++ != NULL)
+ ;
+
+ for (auxv = (Elf32_auxv_t *) envp; auxv->a_type != AT_NULL; auxv++) {
+ if (auxv->a_type == AT_HWCAP) {
+ if (auxv->a_un.a_val & CPU_HAS_LLSC) {
+ arch_flags |= ARCH_FLAG_1;
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
+
+#define ARCH_HAVE_INIT
+
#endif
static struct flist_head *cgroup_list;
static char *cgroup_mnt;
+unsigned long arch_flags = 0;
+
struct io_log *agg_io_log[2];
#define TERMINATE_ALL (-1)
fio_unpin_memory();
}
-int main(int argc, char *argv[])
+int main(int argc, char *argv[], char *envp[])
{
long ps;
+ arch_init(envp);
+
sinit();
init_rand(&__fio_rand_state);