A few fixes for 32-bit compiles

[fio.git] / crc / crc32c-intel.c

diff --git a/crc/crc32c-intel.c b/crc/crc32c-intel.c
index c0abe73ad7a85ac5bb794f3e50b6137b796391df..969a037f942d24e9509b11217fd3123e01658aea 100644 (file)
--- a/crc/crc32c-intel.c
+++ b/crc/crc32c-intel.c
@@ -1,4 +1,11 @@
 #include <inttypes.h>
+#include <string.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include "crc32c.h"
 
 /*
  * Based on a posting to lkml by Austin Zhang <austin.zhang@intel.com>
@@ -11,6 +18,8 @@
  * Volume 2A: Instruction Set Reference, A-M
  */
 
+#ifdef ARCH_HAVE_SSE4_2
+
 #if BITS_PER_LONG == 64
 #define REX_PRE "0x48, "
 #define SCALE_F 8
@@ -64,3 +73,31 @@ uint32_t crc32c_intel(unsigned char const *data, unsigned long length)
 
        return crc;
 }
+
+static void do_cpuid(unsigned int *eax, unsigned int *ebx, unsigned int *ecx,
+                    unsigned int *edx)
+{
+       int id = *eax;
+
+       asm("movl %4, %%eax;"
+           "cpuid;"
+           "movl %%eax, %0;"
+           "movl %%ebx, %1;"
+           "movl %%ecx, %2;"
+           "movl %%edx, %3;"
+               : "=r" (*eax), "=r" (*ebx), "=r" (*ecx), "=r" (*edx)
+               : "r" (id)
+               : "eax", "ebx", "ecx", "edx");
+}
+
+int crc32c_intel_works(void)
+{
+       unsigned int eax, ebx, ecx, edx;
+
+       eax = 1;
+
+       do_cpuid(&eax, &ebx, &ecx, &edx);
+       return (ecx & (1 << 20)) != 0;
+}
+
+#endif /* ARCH_HAVE_SSE */