Change ARCH_X86_64_h to ARCH_X86_64_H

[fio.git] / arch / arch-x86_64.h

diff --git a/arch/arch-x86_64.h b/arch/arch-x86_64.h
index 979c3206185f87334488d60179ff9918e13642cf..a0e8c039c1478ca1d7a24a86e043151f413bd715 100644 (file)
--- a/arch/arch-x86_64.h
+++ b/arch/arch-x86_64.h
@@ -1,7 +1,18 @@
-#ifndef ARCH_X86_64_h
-#define ARCH_X86_64_h
+#ifndef ARCH_X86_64_H
+#define ARCH_X86_64_H
 
-#define ARCH   (arch_x86_64)
+static inline void do_cpuid(unsigned int *eax, unsigned int *ebx,
+                           unsigned int *ecx, unsigned int *edx)
+{
+       asm volatile("cpuid"
+               : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
+               : "0" (*eax), "2" (*ecx)
+               : "memory");
+}
+
+#include "arch-x86-common.h"
+
+#define FIO_ARCH       (arch_x86_64)
 
 #ifndef __NR_ioprio_set
 #define __NR_ioprio_set                251
@@ -18,25 +29,73 @@
 #define __NR_sys_vmsplice      278
 #endif
 
-#ifndef __NR_async_exec
-#define __NR_async_exec                286
-#define __NR_async_wait                287
-#define __NR_umem_add          288
-#define __NR_async_thread      289
+#ifndef __NR_shmget
+#define __NR_shmget             29
+#define __NR_shmat              30
+#define __NR_shmctl             31
+#define __NR_shmdt              67
+#endif
+
+#ifndef __NR_preadv2
+#define __NR_preadv2           327
+#endif
+#ifndef __NR_pwritev2
+#define __NR_pwritev2          328
 #endif
 
-#define        FIO_HUGE_PAGE           2097152
 
-#define FIO_HAVE_SYSLET
+#define        FIO_HUGE_PAGE           2097152
 
 #define nop            __asm__ __volatile__("rep;nop": : :"memory")
-#define read_barrier() asm volatile("lfence":::"memory")
+#define read_barrier() __asm__ __volatile__("lfence":::"memory")
+#define write_barrier()        __asm__ __volatile__("sfence":::"memory")
 
-static inline unsigned long fio_ffz(unsigned long bitmask)
+static inline unsigned long arch_ffz(unsigned long bitmask)
 {
-       __asm__("bsfq %1,%0" :"=r" (bitmask) :"r" (~bitmask));
+       __asm__("bsf %1,%0" :"=r" (bitmask) :"r" (~bitmask));
        return bitmask;
 }
 
+static inline unsigned long long get_cpu_clock(void)
+{
+       unsigned int lo, hi;
+
+       __asm__ __volatile__("rdtsc" : "=a" (lo), "=d" (hi));
+       return ((unsigned long long) hi << 32ULL) | lo;
+}
+
+#define ARCH_HAVE_FFZ
+#define ARCH_HAVE_SSE4_2
+#define ARCH_HAVE_CPU_CLOCK
+
+#define RDRAND_LONG    ".byte 0x48,0x0f,0xc7,0xf0"
+#define RDSEED_LONG    ".byte 0x48,0x0f,0xc7,0xf8"
+#define RDRAND_RETRY   100
+
+static inline int arch_rand_long(unsigned long *val)
+{
+       int ok;
+
+       asm volatile("1: " RDRAND_LONG "\n\t"
+                    "jc 2f\n\t"
+                    "decl %0\n\t"
+                    "jnz 1b\n\t"
+                    "2:"
+                    : "=r" (ok), "=a" (*val)
+                    : "0" (RDRAND_RETRY));
+
+       return ok;
+}
+
+static inline int arch_rand_seed(unsigned long *seed)
+{
+       unsigned char ok;
+
+       asm volatile(RDSEED_LONG "\n\t"
+                       "setc %0"
+                       : "=qm" (ok), "=a" (*seed));
+
+       return 0;
+}
 
 #endif