-#ifndef ARCH_X86_64_h
-#define ARCH_X86_64_h
+#ifndef ARCH_X86_64_H
+#define ARCH_X86_64_H
-#define ARCH (arch_x86_64)
-
-#ifndef __NR_ioprio_set
-#define __NR_ioprio_set 251
-#define __NR_ioprio_get 252
-#endif
-
-#ifndef __NR_fadvise64
-#define __NR_fadvise64 221
-#endif
+static inline void do_cpuid(unsigned int *eax, unsigned int *ebx,
+ unsigned int *ecx, unsigned int *edx)
+{
+ asm volatile("cpuid"
+ : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
+ : "0" (*eax), "2" (*ecx)
+ : "memory");
+}
-#ifndef __NR_sys_splice
-#define __NR_sys_splice 275
-#define __NR_sys_tee 276
-#define __NR_sys_vmsplice 278
-#endif
+#include "arch-x86-common.h" /* IWYU pragma: export */
-#ifndef __NR_async_exec
-#define __NR_async_exec 286
-#define __NR_async_wait 287
-#define __NR_umem_add 288
-#define __NR_async_thread 289
-#endif
+#define FIO_ARCH (arch_x86_64)
#define FIO_HUGE_PAGE 2097152
-#define FIO_HAVE_SYSLET
-
#define nop __asm__ __volatile__("rep;nop": : :"memory")
-#define read_barrier() __asm__ __volatile__("lfence":::"memory")
-#define write_barrier() __asm__ __volatile__("sfence":::"memory")
+#define read_barrier() __asm__ __volatile__("":::"memory")
+#define write_barrier() __asm__ __volatile__("":::"memory")
-static inline unsigned int arch_ffz(unsigned int bitmask)
+static inline unsigned long arch_ffz(unsigned long bitmask)
{
- __asm__("bsfl %1,%0" :"=r" (bitmask) :"r" (~bitmask));
+ __asm__("bsf %1,%0" :"=r" (bitmask) :"r" (~bitmask));
return bitmask;
}
+
+static inline void tsc_barrier(void)
+{
+ __asm__ __volatile__("mfence":::"memory");
+}
+
+static inline unsigned long long get_cpu_clock(void)
+{
+ unsigned int lo, hi;
+
+ __asm__ __volatile__("rdtsc" : "=a" (lo), "=d" (hi));
+ return ((unsigned long long) hi << 32ULL) | lo;
+}
+
#define ARCH_HAVE_FFZ
+#define ARCH_HAVE_SSE4_2
+#define ARCH_HAVE_CPU_CLOCK
-typedef struct {
- unsigned int lock;
-} spinlock_t;
+#define RDRAND_LONG ".byte 0x48,0x0f,0xc7,0xf0"
+#define RDSEED_LONG ".byte 0x48,0x0f,0xc7,0xf8"
+#define RDRAND_RETRY 100
-static inline void spin_lock(spinlock_t *lock)
+static inline int arch_rand_long(unsigned long *val)
{
- short inc = 0x0100;
-
- __asm__ __volatile__("xaddw %w0, %1\n"
- "1:\t"
- "cmpb %h0, %b0\n\t"
- "je 2f\n\t"
- "rep ; nop\n\t"
- "movb %1, %b0\n\t"
- "jmp 1b\n"
- "2:"
- : "+Q" (inc), "+m" (lock->lock)
- :
- : "memory", "cc");
+ int ok;
+
+ asm volatile("1: " RDRAND_LONG "\n\t"
+ "jc 2f\n\t"
+ "decl %0\n\t"
+ "jnz 1b\n\t"
+ "2:"
+ : "=r" (ok), "=a" (*val)
+ : "0" (RDRAND_RETRY));
+
+ return ok;
}
-static inline void spin_unlock(spinlock_t *lock)
+static inline int arch_rand_seed(unsigned long *seed)
{
- __asm__ __volatile__("incb %0"
- : "+m" (lock->lock)
- :
- : "memory", "cc");
+ unsigned char ok;
+
+ asm volatile(RDSEED_LONG "\n\t"
+ "setc %0"
+ : "=qm" (ok), "=a" (*seed));
+
+ return 0;
}
-#define __SPIN_LOCK_UNLOCKED { 0 }
+#define __do_syscall0(NUM) ({ \
+ intptr_t rax; \
+ \
+ __asm__ volatile( \
+ "syscall" \
+ : "=a"(rax) /* %rax */ \
+ : "a"(NUM) /* %rax */ \
+ : "rcx", "r11", "memory" \
+ ); \
+ rax; \
+})
+
+#define __do_syscall1(NUM, ARG1) ({ \
+ intptr_t rax; \
+ \
+ __asm__ volatile( \
+ "syscall" \
+ : "=a"(rax) /* %rax */ \
+ : "a"((NUM)), /* %rax */ \
+ "D"((ARG1)) /* %rdi */ \
+ : "rcx", "r11", "memory" \
+ ); \
+ rax; \
+})
+
+#define __do_syscall2(NUM, ARG1, ARG2) ({ \
+ intptr_t rax; \
+ \
+ __asm__ volatile( \
+ "syscall" \
+ : "=a"(rax) /* %rax */ \
+ : "a"((NUM)), /* %rax */ \
+ "D"((ARG1)), /* %rdi */ \
+ "S"((ARG2)) /* %rsi */ \
+ : "rcx", "r11", "memory" \
+ ); \
+ rax; \
+})
+
+#define __do_syscall3(NUM, ARG1, ARG2, ARG3) ({ \
+ intptr_t rax; \
+ \
+ __asm__ volatile( \
+ "syscall" \
+ : "=a"(rax) /* %rax */ \
+ : "a"((NUM)), /* %rax */ \
+ "D"((ARG1)), /* %rdi */ \
+ "S"((ARG2)), /* %rsi */ \
+ "d"((ARG3)) /* %rdx */ \
+ : "rcx", "r11", "memory" \
+ ); \
+ rax; \
+})
+
+#define __do_syscall4(NUM, ARG1, ARG2, ARG3, ARG4) ({ \
+ intptr_t rax; \
+ register __typeof__(ARG4) __r10 __asm__("r10") = (ARG4); \
+ \
+ __asm__ volatile( \
+ "syscall" \
+ : "=a"(rax) /* %rax */ \
+ : "a"((NUM)), /* %rax */ \
+ "D"((ARG1)), /* %rdi */ \
+ "S"((ARG2)), /* %rsi */ \
+ "d"((ARG3)), /* %rdx */ \
+ "r"(__r10) /* %r10 */ \
+ : "rcx", "r11", "memory" \
+ ); \
+ rax; \
+})
+
+#define __do_syscall5(NUM, ARG1, ARG2, ARG3, ARG4, ARG5) ({ \
+ intptr_t rax; \
+ register __typeof__(ARG4) __r10 __asm__("r10") = (ARG4); \
+ register __typeof__(ARG5) __r8 __asm__("r8") = (ARG5); \
+ \
+ __asm__ volatile( \
+ "syscall" \
+ : "=a"(rax) /* %rax */ \
+ : "a"((NUM)), /* %rax */ \
+ "D"((ARG1)), /* %rdi */ \
+ "S"((ARG2)), /* %rsi */ \
+ "d"((ARG3)), /* %rdx */ \
+ "r"(__r10), /* %r10 */ \
+ "r"(__r8) /* %r8 */ \
+ : "rcx", "r11", "memory" \
+ ); \
+ rax; \
+})
+
+#define __do_syscall6(NUM, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) ({ \
+ intptr_t rax; \
+ register __typeof__(ARG4) __r10 __asm__("r10") = (ARG4); \
+ register __typeof__(ARG5) __r8 __asm__("r8") = (ARG5); \
+ register __typeof__(ARG6) __r9 __asm__("r9") = (ARG6); \
+ \
+ __asm__ volatile( \
+ "syscall" \
+ : "=a"(rax) /* %rax */ \
+ : "a"((NUM)), /* %rax */ \
+ "D"((ARG1)), /* %rdi */ \
+ "S"((ARG2)), /* %rsi */ \
+ "d"((ARG3)), /* %rdx */ \
+ "r"(__r10), /* %r10 */ \
+ "r"(__r8), /* %r8 */ \
+ "r"(__r9) /* %r9 */ \
+ : "rcx", "r11", "memory" \
+ ); \
+ rax; \
+})
+
+#define FIO_ARCH_HAS_SYSCALL
#endif
projects / fio.git / blobdiff