| | 1 | #ifndef ARCH_PPC_H |
| | 2 | #define ARCH_PPC_H |
| | 3 | |
| | 4 | #include <unistd.h> |
| | 5 | #include <stdlib.h> |
| | 6 | #include <sys/types.h> |
| | 7 | #include <sys/wait.h> |
| | 8 | |
| | 9 | #define FIO_ARCH (arch_ppc) |
| | 10 | |
| | 11 | #ifndef __NR_ioprio_set |
| | 12 | #define __NR_ioprio_set 273 |
| | 13 | #define __NR_ioprio_get 274 |
| | 14 | #endif |
| | 15 | |
| | 16 | #ifndef __NR_fadvise64 |
| | 17 | #define __NR_fadvise64 233 |
| | 18 | #endif |
| | 19 | |
| | 20 | #ifndef __NR_sys_splice |
| | 21 | #define __NR_sys_splice 283 |
| | 22 | #define __NR_sys_tee 284 |
| | 23 | #define __NR_sys_vmsplice 285 |
| | 24 | #endif |
| | 25 | |
| | 26 | #define nop do { } while (0) |
| | 27 | |
| | 28 | #ifdef __powerpc64__ |
| | 29 | #define read_barrier() __asm__ __volatile__ ("lwsync" : : : "memory") |
| | 30 | #else |
| | 31 | #define read_barrier() __asm__ __volatile__ ("sync" : : : "memory") |
| | 32 | #endif |
| | 33 | |
| | 34 | #define write_barrier() __asm__ __volatile__ ("sync" : : : "memory") |
| | 35 | |
| | 36 | #ifdef __powerpc64__ |
| | 37 | #define PPC_CNTLZL "cntlzd" |
| | 38 | #else |
| | 39 | #define PPC_CNTLZL "cntlzw" |
| | 40 | #endif |
| | 41 | |
| | 42 | static inline int __ilog2(unsigned long bitmask) |
| | 43 | { |
| | 44 | int lz; |
| | 45 | |
| | 46 | asm (PPC_CNTLZL " %0,%1" : "=r" (lz) : "r" (bitmask)); |
| | 47 | return BITS_PER_LONG - 1 - lz; |
| | 48 | } |
| | 49 | |
| | 50 | static inline int arch_ffz(unsigned long bitmask) |
| | 51 | { |
| | 52 | if ((bitmask = ~bitmask) == 0) |
| | 53 | return BITS_PER_LONG; |
| | 54 | return __ilog2(bitmask & -bitmask); |
| | 55 | } |
| | 56 | |
| | 57 | static inline unsigned int mfspr(unsigned int reg) |
| | 58 | { |
| | 59 | unsigned int val; |
| | 60 | |
| | 61 | asm volatile("mfspr %0,%1": "=r" (val) : "K" (reg)); |
| | 62 | return val; |
| | 63 | } |
| | 64 | |
| | 65 | #define SPRN_TBRL 0x10C /* Time Base Register Lower */ |
| | 66 | #define SPRN_TBRU 0x10D /* Time Base Register Upper */ |
| | 67 | #define SPRN_ATBL 0x20E /* Alternate Time Base Lower */ |
| | 68 | #define SPRN_ATBU 0x20F /* Alternate Time Base Upper */ |
| | 69 | |
| | 70 | static inline unsigned long long get_cpu_clock(void) |
| | 71 | { |
| | 72 | unsigned int tbl, tbu0, tbu1; |
| | 73 | unsigned long long ret; |
| | 74 | |
| | 75 | do { |
| | 76 | if (arch_flags & ARCH_FLAG_1) { |
| | 77 | tbu0 = mfspr(SPRN_ATBU); |
| | 78 | tbl = mfspr(SPRN_ATBL); |
| | 79 | tbu1 = mfspr(SPRN_ATBU); |
| | 80 | } else { |
| | 81 | tbu0 = mfspr(SPRN_TBRU); |
| | 82 | tbl = mfspr(SPRN_TBRL); |
| | 83 | tbu1 = mfspr(SPRN_TBRU); |
| | 84 | } |
| | 85 | } while (tbu0 != tbu1); |
| | 86 | |
| | 87 | ret = (((unsigned long long)tbu0) << 32) | tbl; |
| | 88 | return ret; |
| | 89 | } |
| | 90 | |
| | 91 | #if 0 |
| | 92 | static void atb_child(void) |
| | 93 | { |
| | 94 | arch_flags |= ARCH_FLAG_1; |
| | 95 | get_cpu_clock(); |
| | 96 | _exit(0); |
| | 97 | } |
| | 98 | |
| | 99 | static void atb_clocktest(void) |
| | 100 | { |
| | 101 | pid_t pid; |
| | 102 | |
| | 103 | pid = fork(); |
| | 104 | if (!pid) |
| | 105 | atb_child(); |
| | 106 | else if (pid != -1) { |
| | 107 | int status; |
| | 108 | |
| | 109 | pid = wait(&status); |
| | 110 | if (pid == -1 || !WIFEXITED(status)) |
| | 111 | arch_flags &= ~ARCH_FLAG_1; |
| | 112 | else |
| | 113 | arch_flags |= ARCH_FLAG_1; |
| | 114 | } |
| | 115 | } |
| | 116 | #endif |
| | 117 | |
| | 118 | #define ARCH_HAVE_INIT |
| | 119 | extern int tsc_reliable; |
| | 120 | |
| | 121 | static inline int arch_init(char *envp[]) |
| | 122 | { |
| | 123 | #if 0 |
| | 124 | tsc_reliable = 1; |
| | 125 | atb_clocktest(); |
| | 126 | #endif |
| | 127 | return 0; |
| | 128 | } |
| | 129 | |
| | 130 | #define ARCH_HAVE_FFZ |
| | 131 | |
| | 132 | /* |
| | 133 | * We don't have it on all platforms, lets comment this out until we |
| | 134 | * can handle it more intelligently. |
| | 135 | * |
| | 136 | * #define ARCH_HAVE_CPU_CLOCK |
| | 137 | */ |
| | 138 | |
| | 139 | #endif |
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