| 1 | #ifndef ARCH_ALPHA_H |
| 2 | #define ARCH_ALPHA_H |
| 3 | |
| 4 | #define ARCH (arch_alpha) |
| 5 | |
| 6 | #ifndef __NR_ioprio_set |
| 7 | #define __NR_ioprio_set 442 |
| 8 | #define __NR_ioprio_get 443 |
| 9 | #endif |
| 10 | |
| 11 | #ifndef __NR_fadvise64 |
| 12 | #define __NR_fadvise64 413 |
| 13 | #endif |
| 14 | |
| 15 | #ifndef __NR_sys_splice |
| 16 | #define __NR_sys_splice 468 |
| 17 | #define __NR_sys_tee 470 |
| 18 | #define __NR_sys_vmsplice 471 |
| 19 | #endif |
| 20 | |
| 21 | #define nop do { } while (0) |
| 22 | #define read_barrier() __asm__ __volatile__("mb": : :"memory") |
| 23 | #define writer_barrier() __asm__ __volatile__("wmb": : :"memory") |
| 24 | |
| 25 | typedef struct { |
| 26 | volatile unsigned int lock; |
| 27 | } spinlock_t; |
| 28 | |
| 29 | static inline void spin_lock(spinlock_t *lock) |
| 30 | { |
| 31 | long tmp; |
| 32 | |
| 33 | __asm__ __volatile__("1: ldl_l %0,%1\n" |
| 34 | " bne %0,2f\n" |
| 35 | " lda %0,1\n" |
| 36 | " stl_c %0,%1\n" |
| 37 | " beq %0,2f\n" |
| 38 | " mb\n" |
| 39 | ".subsection 2\n" |
| 40 | "2: ldl %0,%1\n" |
| 41 | " bne %0,2b\n" |
| 42 | " br 1b\n" |
| 43 | ".previous" |
| 44 | : "=&r" (tmp), "=m" (lock->lock) |
| 45 | : "m"(lock->lock) : "memory"); |
| 46 | } |
| 47 | |
| 48 | static inline void spin_unlock(spinlock_t *lock) |
| 49 | { |
| 50 | read_barrier(); |
| 51 | lock->lock = 0; |
| 52 | } |
| 53 | |
| 54 | #endif |