ARM: Use generic assembly nop and barrier code for armv6
[fio.git] / arch / arch-x86_64.h
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1#ifndef ARCH_X86_64_h
2#define ARCH_X86_64_h
3
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4static inline void do_cpuid(unsigned int *eax, unsigned int *ebx,
5 unsigned int *ecx, unsigned int *edx)
6{
7 asm volatile("cpuid"
8 : "=a" (*eax), "=b" (*ebx), "=r" (*ecx), "=d" (*edx)
9 : "0" (*eax), "2" (*ecx)
10 : "memory");
11}
12
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13#include "arch-x86-common.h"
14
cca84643 15#define FIO_ARCH (arch_x86_64)
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16
17#ifndef __NR_ioprio_set
18#define __NR_ioprio_set 251
19#define __NR_ioprio_get 252
20#endif
21
22#ifndef __NR_fadvise64
23#define __NR_fadvise64 221
24#endif
25
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26#ifndef __NR_sys_splice
27#define __NR_sys_splice 275
28#define __NR_sys_tee 276
29#define __NR_sys_vmsplice 278
30#endif
31
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32#define FIO_HUGE_PAGE 2097152
33
db6defc7 34#define nop __asm__ __volatile__("rep;nop": : :"memory")
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35#define read_barrier() __asm__ __volatile__("lfence":::"memory")
36#define write_barrier() __asm__ __volatile__("sfence":::"memory")
ebac4655 37
0ce8b119 38static inline unsigned long arch_ffz(unsigned long bitmask)
8f7e39dd 39{
0ce8b119 40 __asm__("bsf %1,%0" :"=r" (bitmask) :"r" (~bitmask));
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41 return bitmask;
42}
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43
44static inline unsigned long long get_cpu_clock(void)
45{
46 unsigned int lo, hi;
47
48 __asm__ __volatile__("rdtsc" : "=a" (lo), "=d" (hi));
49 return ((unsigned long long) hi << 32ULL) | lo;
50}
51
21df44a2 52#define ARCH_HAVE_FFZ
2f68124f 53#define ARCH_HAVE_SSE4_2
c223da83 54#define ARCH_HAVE_CPU_CLOCK
8f7e39dd 55
ebac4655 56#endif