Commit | Line | Data |
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ebac4655 JA |
1 | #ifndef ARCH_S390_H |
2 | #define ARCH_S390_H | |
3 | ||
cca84643 | 4 | #define FIO_ARCH (arch_s390) |
ebac4655 JA |
5 | |
6 | #ifndef __NR_ioprio_set | |
7 | #define __NR_ioprio_set 282 | |
8 | #define __NR_ioprio_get 283 | |
9 | #endif | |
10 | ||
11 | #ifndef __NR_fadvise64 | |
12 | #define __NR_fadvise64 253 | |
13 | #endif | |
14 | ||
9a9c63f1 JA |
15 | #ifndef __NR_sys_splice |
16 | #define __NR_sys_splice 306 | |
17 | #define __NR_sys_tee 308 | |
18 | #define __NR_sys_vmsplice 309 | |
19 | #endif | |
20 | ||
b12ebc65 | 21 | #define nop asm volatile ("diag 0,0,68" : : : "memory") |
db6defc7 | 22 | #define read_barrier() asm volatile("bcr 15,0" : : : "memory") |
44c47feb | 23 | #define write_barrier() asm volatile("bcr 15,0" : : : "memory") |
ebac4655 | 24 | |
919e789d CE |
25 | /* |
26 | * Fio needs monotonic (never lower), but not strict monotonic (never the same) | |
27 | * so store clock fast is enough | |
28 | */ | |
15cf40b2 DH |
29 | static inline unsigned long long get_cpu_clock(void) |
30 | { | |
31 | unsigned long long clk; | |
32 | ||
919e789d CE |
33 | __asm__ __volatile__("stckf %0" : "=Q" (clk) : : "cc"); |
34 | return clk>>12; | |
15cf40b2 DH |
35 | } |
36 | ||
919e789d CE |
37 | #define ARCH_CPU_CLOCK_CYCLES_PER_USEC 1 |
38 | #define ARCH_HAVE_CPU_CLOCK | |
39 | ||
15cf40b2 DH |
40 | #define ARCH_HAVE_INIT |
41 | extern int tsc_reliable; | |
42 | static inline int arch_init(char *envp[]) | |
43 | { | |
44 | tsc_reliable = 1; | |
45 | return 0; | |
46 | } | |
47 | ||
ebac4655 | 48 | #endif |