arch-ppc.h: Add ilog2 implementation for ppc64
[fio.git] / arch / arch-ppc.h
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ebac4655 1#ifndef ARCH_PPC_H
9ddf9439 2#define ARCH_PPC_H
ebac4655 3
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4#include <unistd.h>
5#include <stdlib.h>
6#include <sys/types.h>
7#include <sys/wait.h>
8
cca84643 9#define FIO_ARCH (arch_ppc)
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10
11#ifndef __NR_ioprio_set
12#define __NR_ioprio_set 273
13#define __NR_ioprio_get 274
14#endif
15
16#ifndef __NR_fadvise64
17#define __NR_fadvise64 233
18#endif
19
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20#ifndef __NR_sys_splice
21#define __NR_sys_splice 283
22#define __NR_sys_tee 284
23#define __NR_sys_vmsplice 285
24#endif
25
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26#define nop do { } while (0)
27
db6defc7 28#ifdef __powerpc64__
44c47feb 29#define read_barrier() __asm__ __volatile__ ("lwsync" : : : "memory")
db6defc7 30#else
44c47feb 31#define read_barrier() __asm__ __volatile__ ("sync" : : : "memory")
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32#endif
33
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34#define write_barrier() __asm__ __volatile__ ("sync" : : : "memory")
35
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36#ifdef __powerpc64__
37#define PPC_CNTLZL "cntlzd"
38#else
39#define PPC_CNTLZL "cntlzw"
40#endif
41
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42static inline int __ilog2(unsigned long bitmask)
43{
44 int lz;
45
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46 asm (PPC_CNTLZL " %0,%1" : "=r" (lz) : "r" (bitmask));
47 return BITS_PER_LONG - 1 - lz;
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48}
49
50static inline int arch_ffz(unsigned long bitmask)
51{
52 if ((bitmask = ~bitmask) == 0)
92060d6c 53 return BITS_PER_LONG;
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54 return __ilog2(bitmask & -bitmask);
55}
5f39d8f7 56
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57static inline unsigned int mfspr(unsigned int reg)
58{
59 unsigned int val;
60
61 asm volatile("mfspr %0,%1": "=r" (val) : "K" (reg));
62 return val;
63}
64
65#define SPRN_TBRL 0x10C /* Time Base Register Lower */
66#define SPRN_TBRU 0x10D /* Time Base Register Upper */
67#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
68#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
69
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70static inline unsigned long long get_cpu_clock(void)
71{
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72 unsigned int tbl, tbu0, tbu1;
73 unsigned long long ret;
5f39d8f7 74
2995607f 75 do {
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76 if (arch_flags & ARCH_FLAG_1) {
77 tbu0 = mfspr(SPRN_ATBU);
78 tbl = mfspr(SPRN_ATBL);
79 tbu1 = mfspr(SPRN_ATBU);
80 } else {
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81 tbu0 = mfspr(SPRN_TBRU);
82 tbl = mfspr(SPRN_TBRL);
83 tbu1 = mfspr(SPRN_TBRU);
4247d1a9 84 }
2995607f 85 } while (tbu0 != tbu1);
5f39d8f7 86
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87 ret = (((unsigned long long)tbu0) << 32) | tbl;
88 return ret;
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89}
90
1b4f8c7f 91#if 0
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92static void atb_child(void)
93{
94 arch_flags |= ARCH_FLAG_1;
95 get_cpu_clock();
96 _exit(0);
97}
98
99static void atb_clocktest(void)
100{
101 pid_t pid;
102
103 pid = fork();
104 if (!pid)
105 atb_child();
62443342 106 else if (pid != -1) {
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107 int status;
108
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109 pid = wait(&status);
110 if (pid == -1 || !WIFEXITED(status))
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111 arch_flags &= ~ARCH_FLAG_1;
112 else
113 arch_flags |= ARCH_FLAG_1;
114 }
115}
1b4f8c7f 116#endif
4247d1a9 117
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118#define ARCH_HAVE_INIT
119extern int tsc_reliable;
4247d1a9 120
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121static inline int arch_init(char *envp[])
122{
ddc0cc31 123#if 0
1b745f55 124 tsc_reliable = 1;
4247d1a9 125 atb_clocktest();
ddc0cc31 126#endif
d20b2ca6 127 return 0;
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128}
129
8f7e39dd 130#define ARCH_HAVE_FFZ
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131
132/*
133 * We don't have it on all platforms, lets comment this out until we
134 * can handle it more intelligently.
135 *
136 * #define ARCH_HAVE_CPU_CLOCK
137 */
8f7e39dd 138
ebac4655 139#endif