[fio.git] / arch / arch-ppc.h

#ifndef ARCH_PPC_H
#define ARCH_PPC_H

#include <unistd.h>
#include <stdlib.h>
#include <sys/types.h>
#include <sys/wait.h>

#define FIO_ARCH	(arch_ppc)

#ifndef __NR_ioprio_set
#define __NR_ioprio_set		273
#define __NR_ioprio_get		274
#endif

#ifndef __NR_fadvise64
#define __NR_fadvise64		233
#endif

#ifndef __NR_sys_splice
#define __NR_sys_splice		283
#define __NR_sys_tee		284
#define __NR_sys_vmsplice	285
#endif

#define nop	do { } while (0)

#ifdef __powerpc64__
#define read_barrier()	__asm__ __volatile__ ("lwsync" : : : "memory")
#else
#define read_barrier()	__asm__ __volatile__ ("sync" : : : "memory")
#endif

#define write_barrier()	__asm__ __volatile__ ("sync" : : : "memory")

static inline int __ilog2(unsigned long bitmask)
{
	int lz;

	asm ("cntlzw %0,%1" : "=r" (lz) : "r" (bitmask));
	return 31 - lz;
}

static inline int arch_ffz(unsigned long bitmask)
{
	if ((bitmask = ~bitmask) == 0)
		return 32;
	return  __ilog2(bitmask & -bitmask);
}

static inline unsigned int mfspr(unsigned int reg)
{
	unsigned int val;

	asm volatile("mfspr %0,%1": "=r" (val) : "K" (reg));
	return val;
}

#define SPRN_TBRL  0x10C /* Time Base Register Lower */
#define SPRN_TBRU  0x10D /* Time Base Register Upper */
#define SPRN_ATBL  0x20E /* Alternate Time Base Lower */
#define SPRN_ATBU  0x20F /* Alternate Time Base Upper */

static inline unsigned long long get_cpu_clock(void)
{
	unsigned int tbl, tbu0, tbu1;
	unsigned long long ret;

	do {
		if (arch_flags & ARCH_FLAG_1) {
			tbu0 = mfspr(SPRN_ATBU);
			tbl = mfspr(SPRN_ATBL);
			tbu1 = mfspr(SPRN_ATBU);
		} else {
			tbu0 = mfspr(SPRN_TBRU);
			tbl = mfspr(SPRN_TBRL);
			tbu1 = mfspr(SPRN_TBRU);
		}
	} while (tbu0 != tbu1);

	ret = (((unsigned long long)tbu0) << 32) | tbl;
	return ret;
}

#if 0
static void atb_child(void)
{
	arch_flags |= ARCH_FLAG_1;
	get_cpu_clock();
	_exit(0);
}

static void atb_clocktest(void)
{
	pid_t pid;

	pid = fork();
	if (!pid)
		atb_child();
	else if (pid != -1) {
		int status;

		pid = wait(&status);
		if (pid == -1 || !WIFEXITED(status))
			arch_flags &= ~ARCH_FLAG_1;
		else
			arch_flags |= ARCH_FLAG_1;
	}
}
#endif

#define ARCH_HAVE_INIT
extern int tsc_reliable;

static inline int arch_init(char *envp[])
{
#if 0
	tsc_reliable = 1;
	atb_clocktest();
#endif
	return 0;
}

#define ARCH_HAVE_FFZ

/*
 * We don't have it on all platforms, lets comment this out until we
 * can handle it more intelligently.
 *
 * #define ARCH_HAVE_CPU_CLOCK
 */

#endif
Commit	Line	Data
ebac4655	1	#ifndef ARCH_PPC_H
9ddf9439	2	#define ARCH_PPC_H
ebac4655	3
4247d1a9 JA	4	#include <unistd.h>
	5	#include <stdlib.h>
	6	#include <sys/types.h>
	7	#include <sys/wait.h>
	8
cca84643	9	#define FIO_ARCH (arch_ppc)
ebac4655 JA	10
	11	#ifndef __NR_ioprio_set
	12	#define __NR_ioprio_set 273
	13	#define __NR_ioprio_get 274
	14	#endif
	15
	16	#ifndef __NR_fadvise64
	17	#define __NR_fadvise64 233
	18	#endif
	19
8756e4d4 JA	20	#ifndef __NR_sys_splice
	21	#define __NR_sys_splice 283
	22	#define __NR_sys_tee 284
	23	#define __NR_sys_vmsplice 285
	24	#endif
	25
ebac4655 JA	26	#define nop do { } while (0)
ebac4655 JA	27
db6defc7	28	#ifdef __powerpc64__
44c47feb	29	#define read_barrier() __asm__ __volatile__ ("lwsync" : : : "memory")
db6defc7	30	#else
44c47feb	31	#define read_barrier() __asm__ __volatile__ ("sync" : : : "memory")
db6defc7 JA	32	#endif
db6defc7 JA	33
44c47feb JA	34	#define write_barrier() __asm__ __volatile__ ("sync" : : : "memory")
44c47feb JA	35
8f7e39dd JA	36	static inline int __ilog2(unsigned long bitmask)
	37	{
	38	int lz;
	39
	40	asm ("cntlzw %0,%1" : "=r" (lz) : "r" (bitmask));
	41	return 31 - lz;
	42	}
	43
	44	static inline int arch_ffz(unsigned long bitmask)
	45	{
	46	if ((bitmask = ~bitmask) == 0)
	47	return 32;
	48	return __ilog2(bitmask & -bitmask);
	49	}
5f39d8f7	50
4247d1a9 JA	51	static inline unsigned int mfspr(unsigned int reg)
	52	{
	53	unsigned int val;
	54
	55	asm volatile("mfspr %0,%1": "=r" (val) : "K" (reg));
	56	return val;
	57	}
	58
	59	#define SPRN_TBRL 0x10C /* Time Base Register Lower */
	60	#define SPRN_TBRU 0x10D /* Time Base Register Upper */
	61	#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
	62	#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
	63
5f39d8f7 CC	64	static inline unsigned long long get_cpu_clock(void)
5f39d8f7 CC	65	{
2995607f JA	66	unsigned int tbl, tbu0, tbu1;
2995607f JA	67	unsigned long long ret;
5f39d8f7	68
2995607f	69	do {
4247d1a9 JA	70	if (arch_flags & ARCH_FLAG_1) {
	71	tbu0 = mfspr(SPRN_ATBU);
	72	tbl = mfspr(SPRN_ATBL);
	73	tbu1 = mfspr(SPRN_ATBU);
	74	} else {
f2dc46ad SN	75	tbu0 = mfspr(SPRN_TBRU);
	76	tbl = mfspr(SPRN_TBRL);
	77	tbu1 = mfspr(SPRN_TBRU);
4247d1a9	78	}
2995607f	79	} while (tbu0 != tbu1);
5f39d8f7	80
2995607f JA	81	ret = (((unsigned long long)tbu0) << 32) \| tbl;
2995607f JA	82	return ret;
5f39d8f7 CC	83	}
5f39d8f7 CC	84
1b4f8c7f	85	#if 0
4247d1a9 JA	86	static void atb_child(void)
	87	{
	88	arch_flags \|= ARCH_FLAG_1;
	89	get_cpu_clock();
	90	_exit(0);
	91	}
	92
	93	static void atb_clocktest(void)
	94	{
	95	pid_t pid;
	96
	97	pid = fork();
	98	if (!pid)
	99	atb_child();
62443342	100	else if (pid != -1) {
4247d1a9 JA	101	int status;
4247d1a9 JA	102
62443342 JA	103	pid = wait(&status);
62443342 JA	104	if (pid == -1 \|\| !WIFEXITED(status))
4247d1a9 JA	105	arch_flags &= ~ARCH_FLAG_1;
	106	else
	107	arch_flags \|= ARCH_FLAG_1;
	108	}
	109	}
1b4f8c7f	110	#endif
4247d1a9	111
1b745f55 JA	112	#define ARCH_HAVE_INIT
1b745f55 JA	113	extern int tsc_reliable;
4247d1a9	114
1b745f55 JA	115	static inline int arch_init(char *envp[])
1b745f55 JA	116	{
ddc0cc31	117	#if 0
1b745f55	118	tsc_reliable = 1;
4247d1a9	119	atb_clocktest();
ddc0cc31	120	#endif
d20b2ca6	121	return 0;
1b745f55 JA	122	}
1b745f55 JA	123
8f7e39dd	124	#define ARCH_HAVE_FFZ
d2d982d3 JA	125
	126	/*
	127	* We don't have it on all platforms, lets comment this out until we
	128	* can handle it more intelligently.
	129	*
	130	* #define ARCH_HAVE_CPU_CLOCK
	131	*/
8f7e39dd	132
ebac4655	133	#endif