Merge branch 'jsonplus2csv' of https://github.com/vincentkfu/fio
[fio.git] / arch / arch-ppc.h
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ebac4655 1#ifndef ARCH_PPC_H
9ddf9439 2#define ARCH_PPC_H
ebac4655 3
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4#include <unistd.h>
5#include <stdlib.h>
6#include <sys/types.h>
7#include <sys/wait.h>
8
cca84643 9#define FIO_ARCH (arch_ppc)
ebac4655 10
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11#define nop do { } while (0)
12
db6defc7 13#ifdef __powerpc64__
44c47feb 14#define read_barrier() __asm__ __volatile__ ("lwsync" : : : "memory")
db6defc7 15#else
44c47feb 16#define read_barrier() __asm__ __volatile__ ("sync" : : : "memory")
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17#endif
18
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19#define write_barrier() __asm__ __volatile__ ("sync" : : : "memory")
20
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21#ifdef __powerpc64__
22#define PPC_CNTLZL "cntlzd"
23#else
24#define PPC_CNTLZL "cntlzw"
25#endif
26
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27static inline int __ilog2(unsigned long bitmask)
28{
29 int lz;
30
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31 asm (PPC_CNTLZL " %0,%1" : "=r" (lz) : "r" (bitmask));
32 return BITS_PER_LONG - 1 - lz;
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33}
34
35static inline int arch_ffz(unsigned long bitmask)
36{
37 if ((bitmask = ~bitmask) == 0)
92060d6c 38 return BITS_PER_LONG;
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39 return __ilog2(bitmask & -bitmask);
40}
5f39d8f7 41
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42static inline unsigned int mfspr(unsigned int reg)
43{
44 unsigned int val;
45
46 asm volatile("mfspr %0,%1": "=r" (val) : "K" (reg));
47 return val;
48}
49
50#define SPRN_TBRL 0x10C /* Time Base Register Lower */
51#define SPRN_TBRU 0x10D /* Time Base Register Upper */
52#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
53#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
54
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55#ifdef __powerpc64__
56static inline unsigned long long get_cpu_clock(void)
57{
58 unsigned long long rval;
59
60 asm volatile(
61 "90: mfspr %0, %1;\n"
62 " cmpwi %0,0;\n"
63 " beq- 90b;\n"
64 : "=r" (rval)
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65 : "i" (SPRN_TBRL)
66 : "cr0");
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67
68 return rval;
69}
70#else
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71static inline unsigned long long get_cpu_clock(void)
72{
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73 unsigned int tbl, tbu0, tbu1;
74 unsigned long long ret;
5f39d8f7 75
2995607f 76 do {
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77 if (arch_flags & ARCH_FLAG_1) {
78 tbu0 = mfspr(SPRN_ATBU);
79 tbl = mfspr(SPRN_ATBL);
80 tbu1 = mfspr(SPRN_ATBU);
81 } else {
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82 tbu0 = mfspr(SPRN_TBRU);
83 tbl = mfspr(SPRN_TBRL);
84 tbu1 = mfspr(SPRN_TBRU);
4247d1a9 85 }
2995607f 86 } while (tbu0 != tbu1);
5f39d8f7 87
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88 ret = (((unsigned long long)tbu0) << 32) | tbl;
89 return ret;
5f39d8f7 90}
1c73ebea 91#endif
5f39d8f7 92
1b4f8c7f 93#if 0
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94static void atb_child(void)
95{
96 arch_flags |= ARCH_FLAG_1;
97 get_cpu_clock();
98 _exit(0);
99}
100
101static void atb_clocktest(void)
102{
103 pid_t pid;
104
105 pid = fork();
106 if (!pid)
107 atb_child();
62443342 108 else if (pid != -1) {
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109 int status;
110
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111 pid = wait(&status);
112 if (pid == -1 || !WIFEXITED(status))
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113 arch_flags &= ~ARCH_FLAG_1;
114 else
115 arch_flags |= ARCH_FLAG_1;
116 }
117}
1b4f8c7f 118#endif
4247d1a9 119
1b745f55 120#define ARCH_HAVE_INIT
24575392 121extern bool tsc_reliable;
4247d1a9 122
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123static inline int arch_init(char *envp[])
124{
ddc0cc31 125#if 0
24575392 126 tsc_reliable = true;
4247d1a9 127 atb_clocktest();
ddc0cc31 128#endif
d20b2ca6 129 return 0;
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130}
131
8f7e39dd 132#define ARCH_HAVE_FFZ
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133
134/*
135 * We don't have it on all platforms, lets comment this out until we
136 * can handle it more intelligently.
137 *
138 * #define ARCH_HAVE_CPU_CLOCK
139 */
8f7e39dd 140
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141/*
142 * Let's have it defined for ppc64
143 */
144
145#ifdef __powerpc64__
146#define ARCH_HAVE_CPU_CLOCK
147#endif
148
ebac4655 149#endif