ppc: disable CPU clock until we can detect whether we have it or not
[fio.git] / arch / arch-arm.h
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1#ifndef ARCH_ARM_H
2#define ARCH_ARM_H
3
cca84643 4#define FIO_ARCH (arch_arm)
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5
6#ifndef __NR_ioprio_set
7#define __NR_ioprio_set 314
8#define __NR_ioprio_get 315
9#endif
10
11#ifndef __NR_fadvise64
12#define __NR_fadvise64 270
13#endif
14
15#ifndef __NR_sys_splice
16#define __NR_sys_splice 340
17#define __NR_sys_tee 342
18#define __NR_sys_vmsplice 343
19#endif
20
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21#if defined (__ARM_ARCH_4__) || defined (__ARM_ARCH_4T__) \
22 || defined (__ARM_ARCH_5__) || defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5TEJ__) \
23 || defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__)
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24#define nop __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t")
25#define read_barrier() __asm__ __volatile__ ("" : : : "memory")
26#define write_barrier() __asm__ __volatile__ ("" : : : "memory")
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27#elif defined(__ARM_ARCH_7A__)
28#define nop __asm__ __volatile__ ("nop")
29#define read_barrier() __sync_synchronize()
30#define write_barrier() __sync_synchronize()
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31#endif
32
33#endif