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2024-01-18	Charlie Jenkins	riscv: Add checksum header Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2024-01-18	Charlie Jenkins	riscv: Add static key for misaligned accesses Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2024-01-18	Charlie Jenkins	asm-generic: Improve csum_fold Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-09	Xiao Wang	riscv: Optimize bitops with Zbb extension Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-09	Xiao Wang	riscv: Rearrange hwcap.h and cpufeature.h Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-09	Palmer Dabbelt	Merge patch "drivers: perf: Do not broadcast to other... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-09	Alexandre Ghiti	drivers: perf: Do not broadcast to other cpus when... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-09	Alexandre Ghiti	drivers: perf: Check find_first_bit() return value Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-09	Palmer Dabbelt	Merge patch series "Linux RISC-V AIA Preparatory Series" Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-09	Anup Patel	of: property: Add fw_devlink support for msi-parent Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-09	Anup Patel	RISC-V: Don't fail in riscv_of_parent_hartid() for... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-08	Palmer Dabbelt	Merge patch series "riscv: Fix set_memory_XX() and... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-08	Alexandre Ghiti	riscv: Fix set_memory_XX() and set_direct_map_XX()... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-08	Alexandre Ghiti	riscv: Don't use PGD entries for the linear mapping Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Evan Green	RISC-V: Probe misaligned access speed in parallel Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Evan Green	RISC-V: Remove __init on unaligned_emulation_finish() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Evan Green	RISC-V: Show accurate per-hart isa in /proc/cpuinfo Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Palmer Dabbelt	RISC-V: Don't rely on positional structure initialization Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Palmer Dabbelt	Merge patch series "riscv: Add remaining module relocations... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Charlie Jenkins	riscv: Add tests for riscv module loading Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Charlie Jenkins	riscv: Add remaining module relocations Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Emil Renner Berthing	riscv: Avoid unaligned access when relocating modules Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Christoph Hellwig	riscv: split cache ops out of dma-noncoherent.c Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Palmer Dabbelt	Merge patch series "riscv: tlb flush improvements" Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Alexandre Ghiti	riscv: Improve flush_tlb_kernel_range() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Alexandre Ghiti	riscv: Make __flush_tlb_range() loop over pte instead... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Alexandre Ghiti	riscv: Improve flush_tlb_range() for hugetlb pages Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Alexandre Ghiti	riscv: Improve tlb_flush() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-07	Andreas Schwab	riscv: select ARCH_PROC_KCORE_TEXT Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-06	Clément Léger	riscv: kernel: Use correct SYM_DATA_*() macro for data Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-06	Clément Léger	riscv: Use SYM_*() assembly macros instead of deprecated... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-06	Clément Léger	riscv: use ".L" local labels in assembly when applicable Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-06	Geert Uytterhoeven	riscv: boot: Fix creation of loader.bin Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-06	Palmer Dabbelt	Merge patch series "riscv: tlb flush improvements" Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-06	Alexandre Ghiti	riscv: Improve flush_tlb_kernel_range() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-06	Alexandre Ghiti	riscv: Make __flush_tlb_range() loop over pte instead... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-06	Alexandre Ghiti	riscv: Improve flush_tlb_range() for hugetlb pages Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-06	Alexandre Ghiti	riscv: Improve tlb_flush() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Jisheng Zhang	riscv: mm: update T-Head memory type definitions Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Palmer Dabbelt	Merge patch series "riscv: vdso.lds.S: some improvement" Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Jisheng Zhang	riscv: vdso.lds.S: remove hardcoded 0x800 .text start... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Jisheng Zhang	riscv: vdso.lds.S: merge .data section into .rodata... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Jisheng Zhang	riscv: vdso.lds.S: drop __alt_start and __alt_end symbols Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Yunhui Cui	riscv: add userland instruction dump to RISC-V splats Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Nam Cao	riscv: kprobes: allow writing to x0 Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Nam Cao	riscv: provide riscv-specific is_trap_insn() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Palmer Dabbelt	Merge patch series "Improve PTDUMP and introduce new... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Yu Chien Peter Lin	riscv: Introduce NAPOT field to PTDUMP Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Yu Chien Peter Lin	riscv: Introduce PBMT field to PTDUMP Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Yu Chien Peter Lin	riscv: Improve PTDUMP to show RSW with non-zero value Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Conor Dooley	RISC-V: capitalise CMO op macros Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Jisheng Zhang	riscv: don't probe unaligned access speed if already... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Jinyu Tang	riscv: defconfig : add CONFIG_MMC_DW for starfive Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Haorong Lu	riscv: signal: handle syscall restart before get_signal Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-05	Palmer Dabbelt	Merge patch series "Add support to handle misaligned... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-02	Andrew Jones	RISC-V: hwprobe: Fix vDSO SIGSEGV Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-02	Lad Prabhakar	riscv: configs: defconfig: Enable configs required... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-02	Palmer Dabbelt	Merge patch series "riscv: SCS support" Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-02	Palmer Dabbelt	Merge patch "riscv: errata: improve T-Head CMO" Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-02	Icenowy Zheng	riscv: errata: prefix T-Head mnemonics with th. Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Clément Léger	riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Clément Léger	riscv: report misaligned accesses emulation to hwprobe Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Clément Léger	riscv: annotate check_unaligned_access_boot_cpu() with... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Clément Léger	riscv: add support for sysctl unaligned_enabled control Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Clément Léger	riscv: add floating point insn support to misaligned... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Clément Léger	riscv: report perf event for misaligned fault Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Clément Léger	riscv: add support for misaligned trap handling in... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Clément Léger	riscv: remove unused functions in traps_misaligned.c Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Palmer Dabbelt	Merge patch series "RISC-V: ACPI improvements" Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Nam Cao	riscv: put interrupt entries into .irqentry.text Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Song Shuai	riscv: mm: Update the comment of CONFIG_PAGE_OFFSET Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Minda Chen	riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Xiao Wang	riscv/mm: Fix the comment for swap pte format Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Tsukasa OI	RISC-V: clarify the QEMU workaround in ISA parser Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Song Shuai	riscv: correct pt_level name via pgtable_l5/4_enabled Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Palmer Dabbelt	RISC-V: Provide pgtable_l5_enabled on rv32 Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Anup Patel	clocksource: timer-riscv: Increase rating of clock_event_dev... Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Anup Patel	clocksource: timer-riscv: Don't enable/disable timer... Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Palmer Dabbelt	Merge patch series "RISC-V: Enable cbo.zero in usermode" Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-11-01	Palmer Dabbelt	Merge patch series "riscv: kexec: cleanup and fixups" Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-27	Sami Tolvanen	lkdtm: Fix CFI_BACKWARD on RISC-V Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-27	Sami Tolvanen	riscv: Use separate IRQ shadow call stacks Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-27	Sami Tolvanen	riscv: Implement Shadow Call Stack Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-27	Sami Tolvanen	riscv: Move global pointer loading to a macro Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-27	Sami Tolvanen	riscv: Deduplicate IRQ stack switching Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-27	Deepak Gupta	riscv: VMAP_STACK overflow detection thread-safe Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-26	Sunil V L	RISC-V: cacheflush: Initialize CBO variables on ACPI... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-26	Sunil V L	RISC-V: ACPI: RHCT: Add function to get CBO block sizes Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-26	Sunil V L	RISC-V: ACPI: Update the return value of acpi_get_rhct() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-26	Sunil V L	RISC-V: ACPI: Enhance acpi_os_ioremap with MMIO remapping Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-12	Alexandre Ghiti	drivers: perf: Fix panic in riscv SBI mmap support Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-12	Alexandre Ghiti	riscv: Fix ftrace syscall handling which are now prefixed... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-12	Jiexun Wang	RISC-V: Fix wrong use of CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-12	Chen Jiahao	riscv: kdump: fix crashkernel reserving problem on... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-12	Song Shuai	riscv: Remove duplicate objcopy flag Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-10-12	Andy Chiu	riscv: signal: fix sigaltstack frame size checking Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-09-27	Lad Prabhakar	riscv: errata: andes: Makefile: Fix randconfig build... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-09-21	Andrew Jones	RISC-V: selftests: Add CBO tests Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-09-21	Andrew Jones	RISC-V: selftests: Convert hwprobe test to kselftest API Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
2023-09-21	Andrew Jones	RISC-V: selftests: Statically link hwprobe test Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>	commit \| commitdiff \| tree
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