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mailbox: arm_mhuv3: Add driver
2024-04-26 Andrew JonesRISC-V: selftests: cbo: Ensure asm operands match constraint...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-04-08 Andrew JonesKVM: selftests: fix supported_flags for riscv
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-02-09 Andrew JonesRISC-V: KVM: Use correct restricted types
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-02-09 Andrew JonesRISC-V: paravirt: Use correct restricted types
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-02-09 Andrew JonesRISC-V: paravirt: steal_time should be static
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-01-30 Andrew JonesKVM: selftests: x86_64: Remove redundant newlines
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-01-29 Andrew JonesKVM: selftests: s390x: Remove redundant newlines
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-01-29 Andrew JonesKVM: selftests: riscv: Remove redundant newlines
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-01-29 Andrew JonesKVM: selftests: aarch64: Remove redundant newlines
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-01-29 Andrew JonesKVM: selftests: Remove redundant newlines
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-01-18 Andrew JonesRISC-V: selftests: cbo: Ensure asm operands match constraints
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-01-11 Andrew Jonesriscv: sbi: Introduce system suspend support
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-01-03 Andrew JonesRISC-V: selftests: Add which-cpus hwprobe test
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-01-03 Andrew JonesRISC-V: hwprobe: Introduce which-cpus flag
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-01-03 Andrew JonesRISC-V: Move the hwprobe syscall to its own file
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2024-01-03 Andrew JonesRISC-V: hwprobe: Clarify cpus size parameter
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-30 Andrew JonesRISC-V: KVM: selftests: Add get-reg-list test for STA...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-30 Andrew JonesRISC-V: KVM: selftests: Add steal_time test support
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-30 Andrew JonesRISC-V: KVM: selftests: Add guest_sbi_probe_extension
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-30 Andrew JonesRISC-V: KVM: selftests: Move sbi_ecall to processor.c
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-30 Andrew JonesRISC-V: KVM: Implement SBI STA extension
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-30 Andrew JonesRISC-V: KVM: Add support for SBI STA registers
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-30 Andrew JonesRISC-V: KVM: Add support for SBI extension registers
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-30 Andrew JonesRISC-V: KVM: Add SBI STA info to vcpu_arch
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-30 Andrew JonesRISC-V: KVM: Add steal-update vcpu request
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-30 Andrew JonesRISC-V: KVM: Add SBI STA extension skeleton
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-30 Andrew JonesRISC-V: paravirt: Implement steal-time support
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-30 Andrew JonesRISC-V: Add SBI STA extension definitions
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-30 Andrew JonesRISC-V: paravirt: Add skeleton for pv-time support
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-29 Andrew JonesRISC-V: KVM: selftests: Treat SBI ext regs like ISA...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-29 Andrew JonesKVM: riscv: selftests: Use register subtypes
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-29 Andrew JonesKVM: riscv: selftests: Add RISCV_SBI_EXT_REG
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-29 Andrew JonesRISC-V: KVM: Make SBI uapi consistent with ISA uapi
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-29 Andrew JonesKVM: riscv: selftests: Drop SBI multi registers
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-29 Andrew JonesRISC-V: KVM: Don't add SBI multi regs in get-reg-list
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-13 Andrew JonesKVM: riscv: selftests: Fix get-reg-list print_reg defaults
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-12-06 Andrew JonesRISC-V: hwprobe: Always use u64 for extension bits
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-11-02 Andrew JonesRISC-V: hwprobe: Fix vDSO SIGSEGV
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-10-12 Andrew JonesKVM: riscv: selftests: get-reg-list print_reg should...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-10-12 Andrew JonesKVM: selftests: Add array order helpers to riscv get...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-10-12 Andrew JonesMAINTAINERS: RISC-V: KVM: Add another kselftests path
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-09-21 Andrew JonesRISC-V: selftests: Add CBO tests
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-09-21 Andrew JonesRISC-V: selftests: Convert hwprobe test to kselftest API
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-09-21 Andrew JonesRISC-V: selftests: Statically link hwprobe test
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-09-21 Andrew JonesRISC-V: hwprobe: Expose Zicboz extension and its block...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-09-21 Andrew JonesRISC-V: Enable cbo.zero in usermode
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-09-21 Andrew JonesRISC-V: Make zicbom/zicboz errors consistent
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-08-09 Andrew JonesKVM: arm64: selftests: Finish generalizing get-reg...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-08-09 Andrew JonesKVM: arm64: selftests: Split get-reg-list test code
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-08-08 Andrew JonesKVM: arm64: selftests: Delete core_reg_fixup
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-08-08 Andrew JonesKVM: arm64: selftests: Rename vcpu_config and add to...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-08-08 Andrew JonesKVM: arm64: selftests: Remove print_reg's dependency...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-08-08 Andrew JonesKVM: arm64: selftests: Drop SVE cap check in print_reg
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-08-08 Andrew JonesKVM: arm64: selftests: Replace str_with_index with...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-08-08 Andrew JonesRISC-V: KVM: Improve vector save/restore functions
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-08-08 Andrew JonesRISC-V: KVM: Improve vector save/restore errors
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-06-06 Andrew JonesRISC-V: KVM: Probe for SBI extension status
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-06-06 Andrew JonesRISC-V: KVM: Convert extension_disabled[] to ext_status[]
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-06-06 Andrew JonesRISC-V: KVM: Rename dis_idx to ext_idx
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-04-29 Andrew JonesRISC-V: Align SBI probe implementation with spec
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-04-26 Andrew JonesRISC-V: hwprobe: Explicity check for -1 in vdso init
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-04-26 Andrew JonesRISC-V: hwprobe: There can only be one first
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-04-21 Andrew JonesRISC-V: KVM: Alphabetize selects
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-03-15 Andrew JonesRISC-V: KVM: Expose Zicboz to the guest
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-03-15 Andrew JonesRISC-V: KVM: Provide UAPI for Zicboz block size
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-03-15 Andrew JonesRISC-V: Use Zicboz in clear_page when available
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-03-15 Andrew JonesRISC-V: cpufeatures: Put the upper 16 bits of patch...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-03-15 Andrew JonesRISC-V: Add Zicboz detection and block size parsing
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-03-15 Andrew Jonesdt-bindings: riscv: Document cboz-block-size
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-03-15 Andrew JonesRISC-V: Factor out body of riscv_init_cbom_blocksize...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-03-15 Andrew JonesRISC-V: alternatives: Support patching multiple insns...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-03-15 Andrew Jonesriscv: cpufeature: Drop errata_list.h and other unused...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-03-15 Andrew Jonesriscv: lib: Include hwcap.h directly
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-03-15 Andrew Jonesriscv: alternatives: Rename errata_id to patch_id
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-03-15 Andrew Jonesriscv: alternatives: Remove unnecessary define and...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-03-15 Andrew Jonesriscv: Rename Kconfig.erratas to Kconfig.errata
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-03-15 Andrew Jonesriscv: Clarify RISCV_ALTERNATIVE help text
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-02-22 Andrew Jonesriscv: hwcap: Don't alphabetize ISA extension IDs
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-02-15 Andrew JonesRISC-V: insn-def: Add I-type insn-def
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
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2023-02-01 Andrew Jonesriscv: KVM: Switch has_svinval() to riscv_has_extension_unli...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2023-02-01 Andrew Jonesriscv: module: Add ADD16 and SUB16 rela types
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-12-13 Andrew Jonesriscv: Apply a static assert to riscv_isa_ext_id
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-12-10 Andrew JonesRISC-V: Ensure Zicbom has a valid block size
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-12-10 Andrew JonesRISC-V: Introduce riscv_isa_extension_check
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-12-10 Andrew JonesRISC-V: Improve use of isa2hwcap[]
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-12-10 Andrew Jonesriscv: Don't duplicate _ALTERNATIVE_CFG* macros
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-12-10 Andrew Jonesriscv: alternatives: Drop the underscores from the...
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-12-10 Andrew Jonesriscv: alternatives: Don't name unused macro parameters
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-12-10 Andrew Jonesriscv: Don't duplicate __ALTERNATIVE_CFG in __ALTERNATIVE_CFG_2
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-10-27 Andrew JonesRISC-V: Fix /proc/cpuinfo cpumask warning
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-10-21 Andrew JonesRISC-V: Fix compilation without RISCV_ISA_ZICBOM
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-10-02 Andrew JonesRISC-V: KVM: Expose Zicbom to the guest
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-10-02 Andrew JonesRISC-V: KVM: Provide UAPI for Zicbom block size
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-10-02 Andrew JonesRISC-V: KVM: Make ISA ext mappings explicit
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-10-02 Andrew Jonesriscv: KVM: Apply insn-def to hlv encodings
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-10-02 Andrew Jonesriscv: KVM: Apply insn-def to hfence encodings
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-10-02 Andrew Jonesriscv: Introduce support for defining instructions
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-10-02 Andrew Jonesriscv: Add X register names to gpr-nums
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-08-17 Andrew Jonesriscv: Ensure isa-ext static keys are writable
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
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2022-06-14 Andrew JonesKVM: selftests: kvm_binary_stats_test: Fix index expressions
Signed-off-by: Andrew Jones <drjones@redhat.com>
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