2018-09-12 | Paulo Zanoni | tracing/Makefile: Fix handling redefinition of CC_FLAGS_FTRACE Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
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2018-07-10 | Paulo Zanoni | drm/i915: use the ICL stolen memory Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180504203252.28048-2-paulo.r.zanoni@intel.com |
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2018-07-10 | Paulo Zanoni | x86/gpu: reserve ICL's graphics stolen memory Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180504203252.28048-1-paulo.r.zanoni@intel.com |
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2018-06-18 | Paulo Zanoni | drm/i915/i915_reg.h: fix the checkpatch MACRO_ARG_PRECEDENCE... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180612235654.7914-4-paulo.r.zanoni@intel.com |
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2018-06-18 | Paulo Zanoni | drm/i915/i915_reg.h: fix the checkpatch SPACE_BEFORE_TAB... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180612235654.7914-3-paulo.r.zanoni@intel.com |
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2018-06-18 | Paulo Zanoni | drm/i915/i915_reg.h: fix the checkpatch SPACING issues Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...patch/msgid/20180618180943.894-1-paulo.r.zanoni@intel.com |
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2018-06-15 | Paulo Zanoni | drm/i915/icl: update VBT's child_device_config flags2... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180614221018.19044-2-paulo.r.zanoni@intel.com |
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2018-06-15 | Paulo Zanoni | drm/i915/icl: implement DVFS for ICL Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180614221018.19044-1-paulo.r.zanoni@intel.com |
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2018-06-14 | Paulo Zanoni | drm/i915/icl: start adding the TBT pll Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180522002558.29262-15-paulo.r.zanoni@intel.com |
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2018-06-14 | Paulo Zanoni | drm/i915/icl: unconditionally init DDI for every port Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180522002558.29262-14-paulo.r.zanoni@intel.com |
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2018-06-14 | Paulo Zanoni | drm/i915/icl: add icelake_get_ddi_pll() Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180522002558.29262-11-paulo.r.zanoni@intel.com |
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2018-06-01 | Paulo Zanoni | drm/i915/icl: introduce tc_port Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180522002558.29262-4-paulo.r.zanoni@intel.com |
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2018-05-17 | Paulo Zanoni | drm/i915: enable the pipe/transcoder/planes later on... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180502215851.30736-1-paulo.r.zanoni@intel.com |
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2018-05-07 | Paulo Zanoni | drm/i915/icl: compute the MG PLL registers Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180328215803.13835-7-paulo.r.zanoni@intel.com |
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2018-05-07 | Paulo Zanoni | drm/i915/icl: compute the combo PHY (DPLL) DP registers Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180328215803.13835-6-paulo.r.zanoni@intel.com |
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2018-05-07 | Paulo Zanoni | drm/i915/icl: compute the combo PHY (DPLL) HDMI registers Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180328215803.13835-5-paulo.r.zanoni@intel.com |
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2018-05-07 | Paulo Zanoni | drm/i915/icl: add basic support for the ICL clocks Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180427231436.9353-1-paulo.r.zanoni@intel.com |
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2018-04-28 | Paulo Zanoni | drm/i915/icl: add definitions for the ICL PLL registers Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180328215803.13835-3-paulo.r.zanoni@intel.com |
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2018-03-28 | Paulo Zanoni | drm/i915/gen11: add support for reading the timestamp... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180109232835.11478-18-paulo.r.zanoni@intel.com |
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2018-03-23 | Paulo Zanoni | drm/i915: protect macro parameters in SWING_SEL_{UPP... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180323195853.4599-1-paulo.r.zanoni@intel.com |
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2018-02-22 | Paulo Zanoni | drm/i915/icl: Add the ICL PCI IDs Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
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2018-02-13 | Paulo Zanoni | drm/i915/icl: implement the display init/uninit sequences Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180205154046.11485-4-paulo.r.zanoni@intel.com |
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2018-02-13 | Paulo Zanoni | drm/i915/icl: add the main CDCLK functions Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180206193346.18272-1-paulo.r.zanoni@intel.com |
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2018-02-13 | Paulo Zanoni | drm/i915/icl: add ICL support to cnl_set_procmon_ref_values Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180205154046.11485-2-paulo.r.zanoni@intel.com |
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2018-01-31 | Paulo Zanoni | drm/i915/icl: allow the reg_read ioctl to read the... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180130134918.32283-10-paulo.r.zanoni@intel.com |
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2018-01-31 | Paulo Zanoni | drm/i915/gen11: fix the SAGV block time for gen11 Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20180130134918.32283-7-paulo.r.zanoni@intel.com |
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2017-10-09 | Paulo Zanoni | drm/i915: avoid division by zero on cnl_calc_wrpll_link Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20171005213842.11423-2-paulo.r.zanoni@intel.com |
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2017-10-09 | Paulo Zanoni | drm/i915: add the BXT and CNL DPLL registers to pipe_config_... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20170922205343.16006-2-paulo.r.zanoni@intel.com |
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2017-08-26 | Paulo Zanoni | drm/i915/cnl: don't hardcode DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20170825194004.26571-1-paulo.r.zanoni@intel.com |
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2017-08-22 | Paulo Zanoni | drm/i915/cnl: extract cnl_set_procmon_ref_values Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
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2017-08-22 | Paulo Zanoni | drm/i915/cnl: simplify cnl_procmon_values handling Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
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2017-08-16 | Paulo Zanoni | drm/i915/gen10: implement gen 10 watermarks calculations Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
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2017-08-10 | Paulo Zanoni | drm/i915/gen10: fix WM latency printing Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
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2017-08-10 | Paulo Zanoni | drm/i915/gen10: fix the gen 10 SAGV block time Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
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2017-08-10 | Paulo Zanoni | drm/i915/gen10+: use the SKL code for reading WM latencies Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
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2017-07-27 | Paulo Zanoni | drm/i915/fbc: add comments to the FBC auxiliary structs Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20170714193822.12121-1-paulo.r.zanoni@intel.com |
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2017-07-27 | Paulo Zanoni | drm/i915: cleanup the CHICKEN_MISC_2 (re)definitions Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...msgid/20170714175228.27019-1-paulo.r.zanoni@intel.com |
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2017-07-06 | Paulo Zanoni | x86/gpu: CNL uses the same GMS values as SKL Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
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2017-06-07 | Paulo Zanoni | drm/i915/cnl: add IS_CNL_REVID macro Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
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2017-03-31 | Paulo Zanoni | drm/i915: make a few DDI functions static Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1490907472-10883-1-git-send-email-paulo.r.zanoni@intel.com |
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2017-03-27 | Paulo Zanoni | drm/i915: kill intel_ddi_pll_select() Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1490209125-20046-2-git-send-email-paulo.r.zanoni@intel.com |
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2017-03-22 | Paulo Zanoni | drm/i915: simplify intel_ddi_pll_select() Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1490209125-20046-1-git-send-email-paulo.r.zanoni@intel.com |
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2017-03-07 | Paulo Zanoni | drm/i915: move the {skl, bxt}_{i, uni}nit_cdclk declarations Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1487712207-17181-1-git-send-email-paulo.r.zanoni@intel.com |
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2017-03-07 | Paulo Zanoni | drm/i915: remove potentially confusing IS_G4X checks Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1487620842-22893-3-git-send-email-paulo.r.zanoni@intel.com |
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2017-01-27 | Paulo Zanoni | drm/i915: make i915_stolen_to_physical() return phys_addr_t Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1485461947-16030-1-git-send-email-paulo.r.zanoni@intel.com |
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2017-01-27 | Paulo Zanoni | x86/gpu: GLK uses the same GMS values as SKL Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1485283642-14401-1-git-send-email-paulo.r.zanoni@intel.com |
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2017-01-04 | Paulo Zanoni | drm/i915: enable FBC on gen9+ too Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1482495839-27041-1-git-send-email-paulo.r.zanoni@intel.com |
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2017-01-04 | Paulo Zanoni | drm/i915: actually drive the BDW reserved IDs Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1483473860-17644-3-git-send-email-paulo.r.zanoni@intel.com |
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2017-01-04 | Paulo Zanoni | drm/i915: more .is_mobile cleanups for BDW Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1483473860-17644-2-git-send-email-paulo.r.zanoni@intel.com |
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2017-01-04 | Paulo Zanoni | drm/i915: fix INTEL_BDW_IDS definition Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1483473860-17644-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-12-20 | Paulo Zanoni | drm/i915: skip the first 4k of stolen memory on everything... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1481727338-9901-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-12-20 | Paulo Zanoni | drm/i915: disable PSR by default on HSW/BDW Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1481662664-18986-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-12-20 | Paulo Zanoni | drm/i915: fully apply WaSkipStolenMemoryFirstPage Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1481808235-27607-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-12-20 | Paulo Zanoni | drm/i915: skip the first 4k of stolen memory on everything... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1481727338-9901-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-12-14 | Paulo Zanoni | drm/i915: disable PSR by default on HSW/BDW Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1481662664-18986-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-11-14 | Paulo Zanoni | drm/i915/fbc: convert intel_fbc.c to use INTEL_GEN() Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1478883461-20201-8-git-send-email-paulo.r.zanoni@intel.com |
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2016-11-14 | Paulo Zanoni | drm/i915/fbc: use drm_atomic_get_existing_crtc_state... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1478883461-20201-6-git-send-email-paulo.r.zanoni@intel.com |
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2016-11-14 | Paulo Zanoni | drm/i915/fbc: inline intel_fbc_can_choose() Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1478883461-20201-5-git-send-email-paulo.r.zanoni@intel.com |
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2016-11-14 | Paulo Zanoni | drm/i915/fbc: extract intel_fbc_can_enable() Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1478883461-20201-4-git-send-email-paulo.r.zanoni@intel.com |
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2016-11-14 | Paulo Zanoni | drm/i915/fbc: replace a loop with drm_atomic_get_existing_cr... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1478883461-20201-3-git-send-email-paulo.r.zanoni@intel.com |
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2016-11-14 | Paulo Zanoni | drm/i915/fbc: move the intel_fbc_can_choose() call... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1478883461-20201-2-git-send-email-paulo.r.zanoni@intel.com |
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2016-11-14 | Paulo Zanoni | drm/i915/gen9: fix the WM memory bandwidth WA for Y... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1478636531-6081-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-28 | Paulo Zanoni | drm/i915/fbc: fix CFB size calculation for gen8+ Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1477065346-13736-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-28 | Paulo Zanoni | drm/i915/gen9: fix watermarks when using the pipe scaler Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1475872138-16194-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-28 | Paulo Zanoni | drm/i915/gen9: fix DDB partitioning for multi-screen... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1475602652-17326-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-24 | Paulo Zanoni | drm/i915/fbc: fix FBC_COMPRESSION_MASK on BDW+ Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1477065346-13736-2-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-24 | Paulo Zanoni | drm/i915/fbc: fix CFB size calculation for gen8+ Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1477065346-13736-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-18 | Paulo Zanoni | drm/i915/gen9: don't call ilk_pipe_pixel_rate() twice... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1475872138-16194-2-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-18 | Paulo Zanoni | drm/i915/gen9: fix watermarks when using the pipe scaler Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1475872138-16194-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-18 | Paulo Zanoni | drm/i915/gen9: look for adjusted_mode in the SAGV check... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1476131459-23763-2-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-18 | Paulo Zanoni | drm/i915/gen9: unconditionally apply the memory bandwidth WA Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1476210338-9797-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-11 | Paulo Zanoni | drm/i915/gen9: fix DDB partitioning for multi-screen... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1475602652-17326-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-10 | Paulo Zanoni | drm/i915/gen9: only add the planes actually affected... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1475177808-29955-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-10 | Paulo Zanoni | drm/i915/gen9: fix the watermark res_blocks value Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-8-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-10 | Paulo Zanoni | drm/i915/gen9: fix plane_blocks_per_line on watermarks... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-7-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-10 | Paulo Zanoni | drm/i915/gen9: minimum scanlines for Y tile is not... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-6-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-10 | Paulo Zanoni | drm/i915/gen9: fix the WaWmMemoryReadLatency implementation Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-5-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-10 | Paulo Zanoni | drm/i915/kbl: KBL also needs to run the SAGV code Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-4-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-10 | Paulo Zanoni | drm/i915: introduce intel_has_sagv() Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-3-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-10 | Paulo Zanoni | drm/i915: SAGV is not SKL-only, so rename a few things Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-2-git-send-email-paulo.r.zanoni@intel.com |
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2016-10-10 | Paulo Zanoni | drm/i915: don't forget to set intel_crtc->dspaddr_offset... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1471644203-23463-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-09-30 | Paulo Zanoni | drm/i915/gen9: only add the planes actually affected... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1475177808-29955-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-09-27 | Paulo Zanoni | drm/i915/skl: tell the user about pre-production hardware Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> |
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2016-09-26 | Paulo Zanoni | drm/i915/gen9: fail the modeset instead of WARNing... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-10-git-send-email-paulo.r.zanoni@intel.com |
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2016-09-26 | Paulo Zanoni | drm/i915/gen9: implement missing case for SKL watermarks... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-9-git-send-email-paulo.r.zanoni@intel.com |
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2016-09-26 | Paulo Zanoni | drm/i915/gen9: fix the watermark res_blocks value Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-8-git-send-email-paulo.r.zanoni@intel.com |
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2016-09-26 | Paulo Zanoni | drm/i915/gen9: fix plane_blocks_per_line on watermarks... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-7-git-send-email-paulo.r.zanoni@intel.com |
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2016-09-26 | Paulo Zanoni | drm/i915/gen9: minimum scanlines for Y tile is not... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-6-git-send-email-paulo.r.zanoni@intel.com |
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2016-09-26 | Paulo Zanoni | drm/i915/gen9: fix the WaWmMemoryReadLatency implementation Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-5-git-send-email-paulo.r.zanoni@intel.com |
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2016-09-26 | Paulo Zanoni | drm/i915/kbl: KBL also needs to run the SAGV code Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-4-git-send-email-paulo.r.zanoni@intel.com |
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2016-09-26 | Paulo Zanoni | drm/i915: introduce intel_has_sagv() Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-3-git-send-email-paulo.r.zanoni@intel.com |
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2016-09-26 | Paulo Zanoni | drm/i915: SAGV is not SKL-only, so rename a few things Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1474578035-424-2-git-send-email-paulo.r.zanoni@intel.com |
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2016-09-22 | Paulo Zanoni | drm/i915: don't forget to set intel_crtc->dspaddr_offset... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1471644203-23463-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-09-22 | Paulo Zanoni | drm/i915/fbc: disable FBC on FIFO underruns Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1473773937-19758-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-08-22 | Paulo Zanoni | drm/i915: Call intel_fbc_pre_update() after pinning... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1471462904-842-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-06-20 | Paulo Zanoni | drm/i915/fbc: sanitize i915.enable_fbc during FBC init Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1460574069-14005-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-06-20 | Paulo Zanoni | drm/i915/fbc: update busy_bits even for GTT and flip... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1459804638-3588-2-git-send-email-paulo.r.zanoni@intel.com |
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2016-02-19 | Paulo Zanoni | drm/i915/fbc: enable FBC by default on HSW and BDW Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1455655643-2535-1-git-send-email-paulo.r.zanoni@intel.com |
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2016-02-04 | Paulo Zanoni | drm/i915/fbc: set fbc->active from the new activation... Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1454101060-23198-3-git-send-email-paulo.r.zanoni@intel.com |
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2016-02-04 | Paulo Zanoni | drm/i915/fbc: unexport the HW level activation functions Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> ...1454101060-23198-2-git-send-email-paulo.r.zanoni@intel.com |
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