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RISC-V: Select GENERIC_SCHED_CLOCK for clocksource drivers
2018-12-21 Anup PatelRISC-V: Select GENERIC_SCHED_CLOCK for clocksource...
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-12-21 Olof JohanssonRISC-V: lib: minor asm cleanup
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-12-21 Palmer DabbeltRISC-V: Move from EARLY_PRINTK to SBI earlycon
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2018-12-21 Nick KossifidisRISC-V: Update Kconfig to better handle CMDLINE
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-12-21 David Abdurachmanovriscv: remove unused variable in ftrace
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-12-21 Yangtao LiRISC-V: add of_node_put()
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-12-21 Atish PatraRISC-V: Fix of_node_* refcount
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-12-21 Andrea Parririscv, atomic: Add #define's for the atomic_{cmp,}xchg_...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-12-17 Anup PatelRISC-V: Remove EARLY_PRINTK support
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-12-17 Anup PatelRISC-V: defconfig: Enable RISC-V SBI earlycon support
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-11-20 Patrick StählinRISC-V: recognize S/U mode bits in print_isa
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-11-20 David Abdurachmanovriscv: add asm/unistd.h UAPI header
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-11-20 David Abdurachmanovriscv: fix warning in arch/riscv/include/asm/module.h
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-11-20 Anup PatelRISC-V: Build flat and compressed kernel images
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-11-20 Olof JohanssonRISC-V: Fix raw_copy_{to,from}_user()
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-11-13 Olof JohanssonRISC-V: Silence some module warnings on 32-bit
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-11-13 Olof JohanssonRISC-V: lib: Fix build error for 64-bit
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-11-13 David Abdurachmanovriscv: add missing vdso_install target
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-11-13 David Abdurachmanovriscv: fix spacing in struct pt_regs
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-11-13 Anup PatelRISC-V: defconfig: Enable printk timestamps
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-11-02 Anup PatelRISC-V: refresh defconfig
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-31 Palmer Dabbeltlib: Remove umoddi3 and udivmoddi4
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-31 Palmer DabbeltMove EM_RISCV into elf-em.h
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-31 Andreas SchwabRISC-V: properly determine hardware caps
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-31 Palmer DabbeltRevert "lib: Add umoddi3 and udivmoddi4 of GCC library...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-31 Palmer DabbeltRevert "RISC-V: Select GENERIC_LIB_UMODDI3 on RV32"
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Palmer DabbeltRISC-V: SMP cleanup and new features
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Palmer DabbeltRISC-V: Fix some RV32 bugs and build failures
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Palmer Dabbeltriscv: Add support to no-FPU systems
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Nick KossifidisRISC-V: Cosmetic menuconfig changes
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Masahiro Yamadariscv: move GCC version check for ARCH_SUPPORTS_INT128...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Christoph HellwigRISC-V: remove the unused return_to_handler export
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Jim WilsonRISC-V: Add futex support.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Jim WilsonRISC-V: Add FP register ptrace support for gdb.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Palmer DabbeltRISC-V: Mask out the F extension on systems without D
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Palmer DabbeltRISC-V: Don't set cacheinfo.{physical_line_partition...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Anup PatelRISC-V: Show IPI stats
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Anup PatelRISC-V: Show CPU ID and Hart ID separately in /proc...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Atish PatraRISC-V: Use Linux logical CPU number instead of hartid
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Atish PatraRISC-V: Add logical CPU indexing for RISC-V
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Atish PatraRISC-V: Use WRITE_ONCE instead of direct access
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Palmer DabbeltRISC-V: Use mmgrab()
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Palmer DabbeltRISC-V: Rename im_okay_therefore_i_am to found_boot_cpu
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Palmer DabbeltRISC-V: Rename riscv_of_processor_hart to riscv_of_processor...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Palmer DabbeltRISC-V: Provide a cleaner raw_smp_processor_id()
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Atish PatraRISC-V: Disable preemption before enabling interrupts
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Palmer DabbeltRISC-V: Comment on the TLB flush in smp_callin()
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Palmer DabbeltRISC-V: Filter ISA and MMU values in cpuinfo
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Palmer DabbeltRISC-V: Don't set cacheinfo.{physical_line_partition...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Anup PatelRISC-V: No need to pass scause as arg to do_IRQ()
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Vincent ChenRISC-V: Avoid corrupting the upper 32-bit of phys_addr_t...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Zong LiRISC-V: Select GENERIC_LIB_UMODDI3 on RV32
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Zong Lilib: Add umoddi3 and udivmoddi4 of GCC library routines
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Zong LiRISC-V: Use swiotlb on RV64 only
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Zong LiRISC-V: Build tishift only on 64-bit
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Alan KaoAuto-detect whether a FPU exists
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Alan KaoAllow to disable FPU support
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Alan KaoCleanup ISA string setting
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Alan KaoRefactor FPU code in signal setup/return procedures
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-23 Alan KaoExtract FPU context operations from entry.S
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-10-02 Atish PatraRISCV: Fix end PFN for low memory
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-09-24 James CowgillRISC-V: include linux/ftrace.h in asm-prototypes.h
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-09-05 Guenter Roeckriscv: Do not overwrite initrd_start and initrd_end
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-28 Palmer DabbeltRISC-V: Use a less ugly workaround for unused variable...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-28 Will Deaconriscv: tlb: Provide definition of tlb_flush() before...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-28 Palmer Dabbeltdt-bindings: riscv,cpu-intc: Cleanups from a missed...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-20 Palmer DabbeltRISC-V: Fix sys_riscv_flush_icache
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2018-08-20 Deepa Dinamaniriscv: Delete asm/compat.h
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-20 Palmer DabbeltRISC-V: Don't use a global include guard for uapi/asm...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-20 Palmer DabbeltRISC-V: Define sys_riscv_flush_icache when SMP=n
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Palmer Dabbeltdt-bindings: interrupt-controller: SiFive Plaform Level...
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Palmer Dabbeltdt-bindings: interrupt-controller: RISC-V local interrupt...
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Atish PatraRISC-V: Fix !CONFIG_SMP compilation error
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Christoph Hellwigirqchip: add a SiFive PLIC driver
 ...driver in the RISC-V tree from Palmer Dabbelt,
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Zong LiRISC-V: Add the directive for alignment of stvec's...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Palmer Dabbeltclocksource: new RISC-V SBI timer driver
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Christoph HellwigRISC-V: implement low-level interrupt handling
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Christoph HellwigRISC-V: add a definition for the SIE SEIE bit
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Christoph HellwigRISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Christoph HellwigRISC-V: simplify software interrupt / IPI code
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Christoph HellwigRISC-V: remove timer leftovers
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Palmer DabbeltRISC-V: Add early printk support via the SBI console
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Jim WilsonRISC-V: Don't increment sepc after breakpoint.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Alex GuoRISC-V: implement __lshrti3.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-08-13 Palmer DabbeltRISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-07-04 Palmer DabbeltRISC-V: Fix the rv32i kernel build
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2018-07-04 Jim WilsonRISC-V: Fix PTRACE_SETREGSET bug.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-07-04 Palmer DabbeltRISC-V: Don't include irq-riscv-intc.h
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-07-04 Rob Herringriscv: remove unnecessary of_platform_populate call
Cc: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-07-04 Andreas SchwabRISC-V: fix R_RISCV_ADD32/R_RISCV_SUB32 relocations
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-07-04 Zong LiRISC-V: Change variable type for 32-bit compatible
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-07-04 Zong LiRISC-V: Add definiion of extract symbol's index and...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-07-04 Zong LiRISC-V: Select GENERIC_UCMPDI2 on RV32I
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-07-04 Zong LiRISC-V: Add conditional macro for zone of DMA32
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-06-11 Palmer DabbeltRISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfig
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-06-11 Palmer DabbeltRISC-V: Make our port sparse-clean
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
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2018-06-11 Palmer DabbeltMAINTAINERS: RISC-V Updates
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-06-11 Andreas SchwabRISC-V: Handle R_RISCV_32 in modules
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-06-11 Alan Kaoriscv/ftrace: Export _mcount when DYNAMIC_FTRACE isn...
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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2018-06-11 Luc Van Oostenryckriscv: add riscv-specific predefines to CHECKFLAGS
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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