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RISC-V: KVM: Probe for SBI extension status
2023-06-06
Andrew Jones
RISC-V: KVM: Probe for SBI extension status
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-06-06
Andrew Jones
RISC-V: KVM: Convert extension_disabled[] to ext_status[]
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-06-06
Andrew Jones
RISC-V: KVM: Rename dis_idx to ext_idx
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-06-06
wchen
RISC-V: KVM: Redirect AMO load/store misaligned traps...
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-06-06
Ye Xingchen
RISC-V: KVM: use bitmap_zero() API
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-04-21
Anup Patel
RISC-V: KVM: Virtualize per-HART AIA CSRs
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-04-21
Anup Patel
RISC-V: KVM: Use bitmap for irqs_pending and irqs_pending_mask
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-04-21
Anup Patel
RISC-V: KVM: Add ONE_REG interface for AIA CSRs
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-04-21
Anup Patel
RISC-V: KVM: Implement subtype for CSR ONE_REG interface
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-04-21
Anup Patel
RISC-V: KVM: Initial skeletal support for AIA
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-04-21
Anup Patel
RISC-V: KVM: Drop the _MASK suffix from hgatp.VMID...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-04-21
Anup Patel
RISC-V: Detect AIA CSRs from ISA string
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-04-21
Anup Patel
RISC-V: Add AIA related CSR defines
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-04-21
Anup Patel
RISC-V: KVM: Allow Zbb extension for Guest/VM
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-04-21
Anup Patel
RISC-V: KVM: Add ONE_REG interface to enable/disable...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-04-21
Andrew Jones
RISC-V: KVM: Alphabetize selects
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-04-21
David Matlack
KVM: RISC-V: Retry fault if vma_lookup() results become...
Tested-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-03-17
Rajnesh Kanwal
riscv/kvm: Fix VM hang in case of timer delta being...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Atish Patra
RISC-V: KVM: Increment firmware pmu events
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Atish Patra
RISC-V: KVM: Support firmware events
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Atish Patra
RISC-V: KVM: Implement perf support without sampling
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Atish Patra
RISC-V: KVM: Implement trap & emulate for hpmcounters
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Atish Patra
RISC-V: KVM: Disable all hpmcounter access for VS/VU...
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Atish Patra
RISC-V: KVM: Make PMU functionality depend on Sscofpmf
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Atish Patra
RISC-V: KVM: Add SBI PMU extension support
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Atish Patra
RISC-V: KVM: Add skeleton support for perf
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Atish Patra
RISC-V: KVM: Modify SBI extension handler to return...
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Atish Patra
RISC-V: KVM: Return correct code for hsm stop function
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Atish Patra
RISC-V: KVM: Define a probe function for SBI extension...
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Atish Patra
RISC-V: Improve SBI PMU extension related definitions
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Atish Patra
perf: RISC-V: Improve privilege mode filtering for...
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Atish Patra
perf: RISC-V: Define helper functions expose hpm counter...
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Andy Chiu
RISC-V: KVM: Redirect illegal instruction traps to...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Anup Patel
RISC-V: KVM: Fix privilege mode setting in kvm_riscv_vcpu_tr...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2023-02-07
Alexandre Ghiti
KVM: RISC-V: Fix wrong usage of PGDIR_SIZE to check...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-12-07
Anup Patel
RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-12-07
Anup Patel
RISC-V: KVM: Save mvendorid, marchid, and mimpid when...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-12-07
Anup Patel
RISC-V: Export sbi_get_mvendorid() and friends
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-12-07
Anup Patel
RISC-V: KVM: Move sbi related struct and functions...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-12-07
Anup Patel
RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-12-07
Anup Patel
RISC-V: KVM: Remove redundant includes of asm/csr.h
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-12-07
Anup Patel
RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-12-07
Anup Patel
RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_con...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-12-07
Christophe JAILLET
RISC-V: KVM: Simplify kvm_arch_prepare_memory_region()
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-12-07
Anup Patel
RISC-V: KVM: Exit run-loop immediately if xfer_to_guest...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-12-07
Bo Liu
RISC-V: KVM: use vma_lookup() instead of find_vma_intersection()
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-12-07
XiakaiPan
RISC-V: KVM: Add exit logic to main.c
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-21
Anup Patel
RISC-V: KVM: Fix kvm_riscv_vcpu_timer_pending() for...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-21
Andrew Jones
RISC-V: Fix compilation without RISCV_ISA_ZICBOM
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Jisheng Zhang
riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Jisheng Zhang
RISC-V: KVM: Use generic guest entry infrastructure
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Jisheng Zhang
RISC-V: KVM: Record number of signal exits as a vCPU...
Signed-off-by: Anup Patel <
anup@brainfault.org
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2022-10-02
Xiu Jianfeng
RISC-V: KVM: add __init annotation to riscv_kvm_init()
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Andrew Jones
RISC-V: KVM: Expose Zicbom to the guest
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Andrew Jones
RISC-V: KVM: Provide UAPI for Zicbom block size
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Andrew Jones
RISC-V: KVM: Make ISA ext mappings explicit
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Mayuresh Chitale
RISC-V: KVM: Allow Guest use Zihintpause extension
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Anup Patel
RISC-V: KVM: Allow Guest use Svinval extension
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Anup Patel
RISC-V: KVM: Use Svinval for local TLB maintenance...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Mayuresh Chitale
RISC-V: Probe Svinval extension form ISA string
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Anup Patel
RISC-V: KVM: Change the SBI specification version to...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Andrew Jones
riscv: KVM: Apply insn-def to hlv encodings
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Andrew Jones
riscv: KVM: Apply insn-def to hfence encodings
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Andrew Jones
riscv: Introduce support for defining instructions
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-10-02
Andrew Jones
riscv: Add X register names to gpr-nums
Reviewed-by: Anup Patel <
anup@brainfault.org
>
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-08-19
Conor Dooley
riscv: kvm: move extern sbi_ext declarations to a header
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-08-19
Conor Dooley
riscv: kvm: vcpu_timer: fix unused variable warnings
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-07-29
Anup Patel
RISC-V: KVM: Add support for Svpbmt inside Guest/VM
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-07-29
Anup Patel
RISC-V: KVM: Use PAGE_KERNEL_IO in kvm_riscv_gstage_ioremap()
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-07-29
Anup Patel
RISC-V: KVM: Add G-stage ioremap() and iounmap() functions
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-07-29
Anup Patel
KVM: Add gfp_custom flag in struct kvm_mmu_memory_cache
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-07-29
Anup Patel
RISC-V: KVM: Add extensible CSR emulation framework
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-07-29
Anup Patel
RISC-V: KVM: Add extensible system instruction emulation...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-07-29
Anup Patel
RISC-V: KVM: Factor-out instruction emulation into...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-07-29
Nikolay Borisov
RISC-V: KVM: move preempt_disable() call in kvm_arch_vcpu_io...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-07-29
Nikolay Borisov
RISC-V: KVM: Make kvm_riscv_guest_timer_init a void...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-07-29
Zhang Jiaming
RISC-V: KVM: Fix variable spelling mistake
Signed-off-by: Anup Patel <
anup@brainfault.org
>
commit
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2022-07-29
Atish Patra
RISC-V: KVM: Improve ISA extension by using a bitmap
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-07-11
Anup Patel
RISC-V: KVM: Fix SRCU deadlock caused by kvm_riscv_check_vcp...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-07-11
Alexandre Ghiti
riscv: Fix missing PAGE_PFN_MASK
Signed-off-by: Anup Patel <
anup@brainfault.org
>
commit
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commitdiff
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2022-06-09
Lukas Bulwahn
MAINTAINERS: Limit KVM RISC-V entry to existing selftests
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-06-09
Julia Lawall
RISC-V: KVM: fix typos in comments
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-05-20
Anup Patel
MAINTAINERS: Update KVM RISC-V entry to cover selftests...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-05-20
Atish Patra
RISC-V: KVM: Introduce ISA extension register
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-05-20
Anup Patel
RISC-V: KVM: Cleanup stale TLB entries when host CPU...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-05-20
Anup Patel
RISC-V: KVM: Add remote HFENCE functions based on VCPU...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-05-20
Anup Patel
RISC-V: KVM: Reduce KVM_MAX_VCPUS value
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-05-20
Anup Patel
RISC-V: KVM: Introduce range based local HFENCE functions
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-05-20
Anup Patel
RISC-V: KVM: Treat SBI HFENCE calls as NOPs
Signed-off-by: Anup Patel <
anup@brainfault.org
>
commit
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2022-05-20
Anup Patel
RISC-V: KVM: Add Sv57x4 mode support for G-stage
Signed-off-by: Anup Patel <
anup@brainfault.org
>
commit
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2022-05-20
Anup Patel
RISC-V: KVM: Use G-stage name for hypervisor page table
Signed-off-by: Anup Patel <
anup@brainfault.org
>
commit
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2022-05-20
Jiapeng Chong
KVM: selftests: riscv: Remove unneeded semicolon
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-05-20
Anup Patel
KVM: selftests: riscv: Improve unexpected guest trap...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
commit
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2022-04-20
Atish Patra
RISC-V: KVM: Restrict the extensions that can be disabled
Signed-off-by: Anup Patel <
anup@brainfault.org
>
commit
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commitdiff
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2022-04-20
Atish Patra
RISC-V: KVM: Remove 's' & 'u' as valid ISA extension
Signed-off-by: Anup Patel <
anup@brainfault.org
>
commit
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2022-04-09
Heiko Stuebner
RISC-V: KVM: include missing hwcap.h into vcpu_fp
Signed-off-by: Anup Patel <
anup@brainfault.org
>
commit
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2022-04-09
Anup Patel
KVM: selftests: riscv: Fix alignment of the guest_hang...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-04-09
Anup Patel
KVM: selftests: riscv: Set PTE A and D bits in VS-stage...
Signed-off-by: Anup Patel <
anup@brainfault.org
>
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2022-04-09
Anup Patel
RISC-V: KVM: Don't clear hgatp CSR in kvm_arch_vcpu_put()
Signed-off-by: Anup Patel <
anup@brainfault.org
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2022-03-11
Anup Patel
RISC-V: KVM: Implement SBI HSM suspend call
Signed-off-by: Anup Patel <
anup@brainfault.org
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