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arm64: Avoid cpus_have_const_cap() for ARM64_WORKAROUND_REPEAT_TLBI
2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_WORKAROUND_REPE...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_WORKAROUND_NVID...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_WORKAROUND_CAVI...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_WORKAROUND_2645198
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_WORKAROUND_1742098
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_WORKAROUND_1542419
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_WORKAROUND_843419
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_UNMAP_KERNEL_AT_EL0
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_{SVE,SME...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_SPECTRE_V2
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_SSBS
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_MTE
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_HAS_TLB_RANGE
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_HAS_WFXT
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_HAS_RNG
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_HAS_EPAN
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_HAS_PAN
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_HAS_GIC_PRIO_MA...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_HAS_DIT
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_HAS_CNP
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_HAS_CACHE_DIC
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_HAS_BTI
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_HAS_ARMv8_4_TTL
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Avoid cpus_have_const_cap() for ARM64_HAS_{ADDRESS...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Use a positive cpucap for FP/SIMD
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Rename SVE/SME cpu_enable functions
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Use build-time assertions for cpucap ordering
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Explicitly save/restore CPACR when probing SVE...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: kvm: Use cpus_have_final_cap() explicitly
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Split kpti_install_ng_mappings()
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Fixup user features at boot time
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Rework setup_cpu_features()
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Add cpus_have_final_boot_cap()
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Add cpucap_is_possible()
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64: Factor out cpucap definitions
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandarm64/arm: xen: enlighten: Fix KPTI checks
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-10-16 Mark Rutlandclocksource/drivers/arm_arch_timer: Initialize evtstrm...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-08-17 Mark Brownarm64/ptrace: Ensure that the task sees ZT writes on...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-08-17 Mark Brownarm64/ptrace: Ensure that SME is set up for target...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-08-04 Mark Brownarm64/fpsimd: Sync and zero pad FPSIMD state for streaming SVE
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-08-04 Mark Brownarm64/fpsimd: Sync FPSIMD state with SVE for SME only...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-08-04 Mark Brownarm64/ptrace: Don't enable SVE when setting streaming SVE
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-08-03 Mark Brownarm64/ptrace: Flush FP state when setting ZT0
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-08-03 Mark Brownarm64/fpsimd: Clear SME state in the target task when...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-07-28 Guanghui FengACPI/IORT: Remove erroneous id_count check in iort_node_get_...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-07-26 Mark Brownarm64/sme: Set new vector length before reallocating
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-07-26 Mark Brownarm64/fpsimd: Don't flush SME register hardware state...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-29 Will Deaconarm64: sme: Use STR P to clear FFR context field in...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-23 Catalin MarinasMerge branch 'for-next/feat_s1pie' into for-next/core
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2023-06-23 Catalin MarinasMerge branches 'for-next/kpti', 'for-next/missing-proto...
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2023-06-23 Mark Brownkselftest/arm64: Add a test case for TPIDR2 restore
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-23 Mark Brownarm64/signal: Restore TPIDR2 register rather than memory...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-21 Mark Rutlandarm64: alternatives: make clean_dcache_range_nopatch...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-21 Chaitanya S PrakashDocumentation/arm64: Add ptdump documentation
[catalin.marinas@arm.com: various minor fixups; sorted...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-21 Song Shuaiarm64: hibernate: remove WARN_ON in save_processor_state
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-21 Mark Brownkselftest/arm64: Log signal code and address for unexpected...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-16 Mark Brownarm64/fpsimd: Exit streaming mode when flushing tasks
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-15 Mark Rutlandarm64: mm: fix VA-range sanity check
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-15 Jamie Ilesarm64/mm: remove now-superfluous ISBs from TTBR writes
[catalin.marinas@arm.com: rename __cpu_set_reserved_ttbr0...
[catalin.marinas@arm.com: move the cpu_set_reserved_ttbr0_nosy...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Jose MarinhoDocumentation/arm64: Update ACPI tables from BBR
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Jose MarinhoDocumentation/arm64: Update references in arm-acpi
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Jose MarinhoDocumentation/arm64: Update ARM and arch reference
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Russell Kingarm64: consolidate rox page protection logic
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Anshuman Khandualarm64/sysreg: Convert TRBIDR_EL1 register to automatic...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Anshuman Khandualarm64/sysreg: Convert TRBTRG_EL1 register to automatic...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Anshuman Khandualarm64/sysreg: Convert TRBMAR_EL1 register to automatic...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Anshuman Khandualarm64/sysreg: Convert TRBSR_EL1 register to automatic...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Anshuman Khandualarm64/sysreg: Convert TRBBASER_EL1 register to automatic...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Anshuman Khandualarm64/sysreg: Convert TRBPTR_EL1 register to automatic...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Anshuman Khandualarm64/sysreg: Convert TRBLIMITR_EL1 register to automatic...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Anshuman Khandualarm64/sysreg: Rename TRBIDR_EL1 fields per auto-gen...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Anshuman Khandualarm64/sysreg: Rename TRBTRG_EL1 fields per auto-gen...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Anshuman Khandualarm64/sysreg: Rename TRBMAR_EL1 fields per auto-gen...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Anshuman Khandualarm64/sysreg: Rename TRBSR_EL1 fields per auto-gen...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Anshuman Khandualarm64/sysreg: Rename TRBBASER_EL1 fields per auto-gen...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Anshuman Khandualarm64/sysreg: Rename TRBPTR_EL1 fields per auto-gen...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-14 Anshuman Khandualarm64/sysreg: Rename TRBLIMITR_EL1 fields per auto...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-13 Baoquan Hearm64: add kdump.rst into index.rst
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-09 Baoquan HeDocumentation: add kdump.rst to present crashkernel...
[catalin.marinas@arm.com: rewrote some sentences, removed...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-09 Baoquan Hearm64: kdump: simplify the reservation behaviour of...
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-08 Youngmin Namarm64: set __exception_irq_entry with __irq_entry as...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-08 Sudeep HollaACPI: bus: Consolidate all arm specific initialisation...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-07 Guo Huiarm64: syscall: unmask DAIF for tracing status
[catalin.marinas@arm.com: updated comment with Mark's...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-07 Mark Rutlandarm64: cpufeature: fold cpus_set_cap() into update_cpu_capab...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-07 Mark Rutlandarm64: cpufeature: use cpucap naming
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-07 Mark Rutlandarm64: alternatives: use cpucap naming
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-07 Mark Rutlandarm64: standardise cpucap bitmap names
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-06 Mark Brownarm64/sysreg: Convert OSECCR_EL1 to automatic generation
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-06 Mark Brownarm64/sysreg: Convert OSDTRTX_EL1 to automatic generation
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-06 Mark Brownarm64/sysreg: Convert OSDTRRX_EL1 to automatic generation
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-06 Mark Brownarm64/sysreg: Convert OSLAR_EL1 to automatic generation
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-06 Mark Brownarm64/sysreg: Standardise naming of bitfield constants...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-06 Mark Brownarm64/sysreg: Convert MDSCR_EL1 to automatic register...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-06 Mark Brownarm64/sysreg: Convert MDCCINT_EL1 to automatic register...
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-06 Mark Rutlandarm64: module: rework module VA range selection
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-06 Mark Rutlandarm64: module: mandate MODULE_PLTS
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-06 Mark Rutlandarm64: module: move module randomization to module.c
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-06 Mark Rutlandarm64: kaslr: split kaslr/module initialization
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-06 Mark Rutlandarm64: kasan: remove !KASAN_VMALLOC remnants
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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2023-06-06 Mark Rutlandarm64: module: remove old !KASAN_VMALLOC logic
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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