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RISC-V: Fix a race condition during kernel stack overflow
2022-12-01
Palmer Dabbelt
RISC-V: Fix a race condition during kernel stack overflow
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2022-11-30
Palmer Dabbelt
Merge patch series "riscv: kexec: Fxiup crash_save...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-11-30
Guo Ren
riscv: kexec: Fixup crash_smp_send_stop without multi...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-11-30
Guo Ren
riscv: kexec: Fixup irq controller broken in kexec...
Cc:
Palmer Dabbelt
<palmer@rivosinc.com>
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-11-30
Björn Töpel
riscv: mm: Proper page permissions after initmem free
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-11-30
Jisheng Zhang
riscv: vdso: fix section overlapping under some conditions
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-11-30
Jisheng Zhang
riscv: fix race when vmap stack overflow
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-11-29
Alexandre Ghiti
riscv: Sync efi page table's kernel mappings before...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-11-28
Samuel Holland
riscv: Fix NR_CPUS range conditions
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-11-10
Nathan Chancellor
RISC-V: vdso: Do not add missing symbols to version...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-11-10
Conor Dooley
riscv: fix reserved memory setup
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-11-10
Jisheng Zhang
riscv: vdso: fix build with llvm
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-11-10
Jisheng Zhang
riscv: process: fix kernel info leakage
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-28
Emil Renner Berthing
riscv: dts: sifive unleashed: Add PWM controlled LEDs
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-27
Andrew Jones
RISC-V: Fix /proc/cpuinfo cpumask warning
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-27
Palmer Dabbelt
Merge patch series "Fix RISC-V toolchain extension...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-27
Conor Dooley
riscv: fix detection of toolchain Zihintpause support
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-27
Conor Dooley
riscv: fix detection of toolchain Zicbom support
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-27
Qinglin Pan
riscv: mm: add missing memcpy in kasan_init
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-26
Palmer Dabbelt
MAINTAINERS: git://github.com -> https://github.com...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-26
Jisheng Zhang
riscv: jump_label: mark arguments as const to satisfy...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Conor Dooley
MAINTAINERS: add RISC-V's patchwork
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Maciej W. Rozycki
RISC-V: Make port I/O string accessors actually work
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Palmer Dabbelt
RISC-V: Add mvendorid, marchid, and mimpid to /proc...
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2022-10-13
Palmer Dabbelt
RISC-V: Make mmap() with PROT_WRITE imply PROT_READ
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Conor Dooley
riscv: enable software resend of irqs
Acked-by:
Palmer Dabbelt
<palmer@rivosinc.com>
Tested-by:
Palmer Dabbelt
<palmer@rivosinc.com> # on QEMU
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Palmer Dabbelt
RISC-V: Re-enable counter access from userspace
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Jisheng Zhang
riscv: vdso: fix NULL deference in vdso_join_timens...
Suggested-by:
Palmer Dabbelt
<palmer@rivosinc.com>
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Palmer Dabbelt
Merge patch series "Use composable cache instead of...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Greentime Hu
riscv: Add cache information in AUX vector
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Zong Li
soc: sifive: ccache: define the macro for the register...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Ben Dooks
soc: sifive: ccache: use pr_fmt() to remove CCACHE...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Ben Dooks
soc: sifive: ccache: reduce printing on init
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Zong Li
soc: sifive: ccache: determine the cache level from dts
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Greentime Hu
soc: sifive: ccache: Rename SiFive L2 cache to Composable...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Zong Li
dt-bindings: sifive-ccache: change Sifive L2 cache...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Palmer Dabbelt
Merge patch series "Some style cleanups for recent...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Heiko Stuebner
riscv: check for kernel config option in t-head memory...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Heiko Stuebner
riscv: use BIT() marco for cpufeature probing
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Heiko Stuebner
riscv: use BIT() macros in t-head errata init
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Heiko Stuebner
riscv: drop some idefs from CMO initialization
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Heiko Stuebner
riscv: cleanup svpbmt cpufeature probing
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Fangrui Song
riscv: Pass -mno-relax only on lld < 15.0.0
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Palmer Dabbelt
RISC-V: Avoid dereferening NULL regs in die()
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Palmer Dabbelt
Merge patch series "Fix dt-validate issues on qemu...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Conor Dooley
dt-bindings: riscv: add new riscv,isa strings for emulators
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Conor Dooley
dt-bindings: interrupt-controller: sifive,plic: add...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-13
Conor Dooley
dt-bindings: timer: sifive,clint: add legacy riscv...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-12
Palmer Dabbelt
Merge tag 'dt-for-palmer-v6.1-mw1' of git://git.kernel...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-12
Palmer Dabbelt
doc: RISC-V: Document that misaligned accesses are...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-12
Wenting Zhang
riscv: always honor the CONFIG_CMDLINE_FORCE when parsing dtb
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-11
Conor Dooley
dt-bindings: riscv: update microchip.yaml's maintainership
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-11
Conor Dooley
MAINTAINERS: update polarfire soc clock binding
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-07
Jisheng Zhang
riscv: enable THP_SWAP for RV64
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-07
Palmer Dabbelt
RISC-V: Print SSTC in canonical order
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-06
Jisheng Zhang
riscv: compat: s/failed/unsupported if compat mode...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-04
Anup Patel
RISC-V: Increase range and default value of NR_CPUS
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-10-04
Anup Patel
RISC-V: Add mvendorid, marchid, and mimpid to /proc...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-09-23
Anup Patel
cpuidle: riscv-sbi: Fix CPU_PM_CPU_IDLE_ENTER_xyz(...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-09-22
Andrew Bresticker
riscv: Allow PROT_WRITE-only mmap()
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-09-22
Andrew Bresticker
riscv: Make VM_WRITE imply VM_READ
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-09-17
Palmer Dabbelt
RISC-V: Avoid coupling the T-Head CMOs and Zicbom
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-09-17
Al Viro
riscv: fix a nasty sigreturn bug...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-09-17
Heiko Stuebner
riscv: make t-head erratas depend on MMU
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-09-17
Randy Dunlap
riscv: fix RISCV_ISA_SVPBMT kconfig dependency warning
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-09-13
Palmer Dabbelt
RISC-V: Clean up the Zicbom block size probing
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-09-08
Sergey Matyukevich
perf: RISC-V: fix access beyond allocated array
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-09-08
Sergey Matyukevich
perf: RISC-V: throttle perf events
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-09-08
Sergey Matyukevich
perf: RISC-V: exclude invalid pmu counters from SBI...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-09-03
Palmer Dabbelt
Merge tag 'dt-fixes-for-palmer-6.0-rc4' of git://git...
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2022-08-26
Heinrich Schuchardt
riscv: enable CD-ROM file systems in defconfig
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-25
Palmer Dabbelt
Merge branch 'riscv-variable_fixes_without_kvm' of...
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2022-08-25
Palmer Dabbelt
Merge tag 'dt-fixes-for-palmer-6.0-rc3' of git://git...
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2022-08-18
Conor Dooley
riscv: traps: add missing prototype
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-18
Conor Dooley
riscv: signal: fix missing prototype warning
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-18
Conor Dooley
perf: riscv legacy: fix kerneldoc comment warning
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-18
Palmer Dabbelt
Merge tag 'riscv-topo-on-6.0-rc1' of https://git.kernel...
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2022-08-17
Andrew Jones
riscv: Ensure isa-ext static keys are writable
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-12
Atul Khare
dt-bindings: gpio: sifive: add gpio-line-names
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-12
Jason A. Donenfeld
wireguard: selftests: set CONFIG_NONPORTABLE on riscv32
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-12
Atish Patra
RISC-V: KVM: Support sstc extension
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-12
Palmer Dabbelt
perf: riscv_pmu{,_sbi}: Miscallenous improvement &...
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2022-08-11
Atish Patra
RISC-V: Improve SBI definitions
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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commitdiff
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2022-08-11
Atish Patra
RISC-V: Move counter info definition to sbi header...
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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commitdiff
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2022-08-11
Atish Patra
RISC-V: Fix SBI PMU calls for RV32
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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commitdiff
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2022-08-11
Atish Patra
RISC-V: Update user page mapping only once during start
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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commitdiff
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2022-08-11
Atish Patra
RISC-V: Fix counter restart during overflow for RV32
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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commitdiff
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tree
2022-08-11
Palmer Dabbelt
RISC-V: Add Sstc extension support
commit
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2022-08-11
Atish Patra
RISC-V: Prefer sstc extension if available
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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commitdiff
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2022-08-11
Atish Patra
RISC-V: Enable sstc extension parsing from DT
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-11
Atish Patra
RISC-V: Add SSTC extension CSR details
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-11
Yipeng Zou
riscv:uprobe fix SR_SPIE set/clear handling
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-11
Conor Dooley
dt-bindings: riscv: fix SiFive l2-cache's cache-sets
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-11
Conor Dooley
riscv: ensure cpu_ops_sbi is declared
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-11
Ben Dooks
RISC-V: cpu_ops_spinwait.c should include head.h
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-11
Ben Dooks
RISC-V: Declare cpu_ops_spinwait in <asm/cpu_ops.h>
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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commitdiff
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2022-08-11
Mark Kettenis
riscv: dts: starfive: correct number of external interrupts
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
commit
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commitdiff
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tree
2022-08-11
Emil Renner Berthing
riscv: dts: sifive unmatched: Add PWM controlled LEDs
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
commit
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commitdiff
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tree
2022-08-11
Masahiro Yamada
riscv/purgatory: Omit use of bin2c
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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2022-08-11
Masahiro Yamada
riscv/purgatory: hard-code obj-y in Makefile
Signed-off-by:
Palmer Dabbelt
<palmer@rivosinc.com>
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