From e89d890c1b4a29fd1871f9ce21e9a94720a10e98 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Thu, 9 Mar 2023 17:05:47 -0500 Subject: [PATCH] drm/amd/display: update dio for two pixel per container case [why] Processing rate of the DP encoder, must be programmed to be the same as DIG_FIFO_OUTPUT_ PROCESSING_MODE in DP mode 0: 1 pixel per cycle 1: 2 pixel per cycle Reviewed-by: Alvin Lee Acked-by: Qingqing Zhuo Signed-off-by: Charlene Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c index c72448125976..89de64f18040 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c @@ -286,6 +286,7 @@ static void enc32_stream_encoder_dp_unblank( uint32_t n_vid = 0x8000; uint32_t m_vid; uint32_t n_multiply = 0; + uint32_t pix_per_cycle = 0; uint64_t m_vid_l = n_vid; /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ @@ -320,6 +321,10 @@ static void enc32_stream_encoder_dp_unblank( REG_UPDATE_2(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1, DP_VID_N_MUL, n_multiply); + + REG_UPDATE(DP_PIXEL_FORMAT, + DP_PIXEL_PER_CYCLE_PROCESSING_MODE, + pix_per_cycle); } /* make sure stream is disabled before resetting steer fifo */ -- 2.25.1