From e64c22cc2e6177a5ff59eee394cf4f4dd2f0ed91 Mon Sep 17 00:00:00 2001 From: Ilkka Koskinen Date: Thu, 5 Dec 2024 06:19:13 +0000 Subject: [PATCH] perf/dwc_pcie: Fix the event numbers According to Databook, L1 aux is event number 0x08 and TX L0s and RX L0S is 0x09. Fix the event numbers for the two events. Signed-off-by: Ilkka Koskinen Reviewed-by: Shuai Xue Link: https://lore.kernel.org/r/20241205061914.5568-2-ilkka@os.amperecomputing.com Signed-off-by: Will Deacon --- drivers/perf/dwc_pcie_pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c index 9cbea9675e21..890cf3bb43a2 100644 --- a/drivers/perf/dwc_pcie_pmu.c +++ b/drivers/perf/dwc_pcie_pmu.c @@ -199,8 +199,8 @@ static struct attribute *dwc_pcie_pmu_time_event_attrs[] = { DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L1_1, 0x05), DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L1_2, 0x06), DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(CFG_RCVRY, 0x07), - DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(TX_RX_L0S, 0x08), - DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L1_AUX, 0x09), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L1_AUX, 0x08), + DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(TX_RX_L0S, 0x09), /* Group #1 */ DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(tx_pcie_tlp_data_payload, 0x20), -- 2.25.1