From da1d515eb1692e87422caefb80799bd716070bbc Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 21 Mar 2025 14:51:14 +0200 Subject: [PATCH] drm/i915/gvt: use hardcoded reference clocks MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Usually I'd argue hardcoding values is the wrong thing to do, but in this case, GVT looking deep into the guts of the DPLL manager for the reference clocks is worse. This is done for BDW and BXT only, and there shouldn't be any reason to try to be so dynamic about it. This helps reduce the direct pokes at display guts from non-display code. Cc: Ville Syrjälä Reviewed-by: Zhenyu Wang Link: https://lore.kernel.org/r/20250321125114.750062-1-jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gvt/handlers.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 02f45929592e..e6e9010462e3 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -514,7 +514,7 @@ static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) switch (wrpll_ctl & WRPLL_REF_MASK) { case WRPLL_REF_PCH_SSC: - refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.ssc; + refclk = 135000; break; case WRPLL_REF_LCPLL: refclk = 2700000; @@ -545,7 +545,7 @@ out: static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) { u32 dp_br = 0; - int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc; + int refclk = 100000; enum dpio_phy phy = DPIO_PHY0; enum dpio_channel ch = DPIO_CH0; struct dpll clock = {}; -- 2.25.1