From d7b4832cbeb85075293b1211a9c89fad4fdda1f1 Mon Sep 17 00:00:00 2001 From: Vinay Belgaumkar Date: Thu, 9 Nov 2023 11:21:48 -0800 Subject: [PATCH] drm/i915: Read a shadowed mmio register for ggtt flush We read RENDER_HEAD as a part of the flush. If GT is in deeper sleep states, this could lead to read errors since we are not using a forcewake. Safer to read a shadowed register instead. Cc: John Harrison Cc: Daniele Ceraolo Spurio Signed-off-by: Vinay Belgaumkar Reviewed-by: Radhakrishna Sripada Signed-off-by: John Harrison Link: https://patchwork.freedesktop.org/patch/msgid/20231109192148.475156-1-vinay.belgaumkar@intel.com --- drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index ed32bf5b1546..ea814ea5f700 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -451,7 +451,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt) spin_lock_irqsave(&uncore->lock, flags); intel_uncore_posting_read_fw(uncore, - RING_HEAD(RENDER_RING_BASE)); + RING_TAIL(RENDER_RING_BASE)); spin_unlock_irqrestore(&uncore->lock, flags); } } -- 2.25.1