From d01e09a9f7cd4fb5a947e3dc718242b51b581615 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 18 Mar 2025 22:08:46 +0100 Subject: [PATCH] arm64: dts: rockchip: Add gmac phy reset GPIO to QNAP TS433 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit While looking through the vendor U-Boot code Heiko spotted that a SoC GPIO is connected to the ethernet phy's reset pin. Add the respective reset-gpios property with pinmuxing for the GPIO to the phy node. Signed-off-by: Uwe Kleine-König Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/49f66206fccc714a8745b9ac35247615ad5cc369.1742331667.git.ukleinek@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts index 70e88769e21c..411f8ac7994b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts @@ -485,6 +485,10 @@ /* Motorcomm YT8521 phy */ compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x3>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; }; }; @@ -557,6 +561,12 @@ }; &pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + keys { copy_button_pin: copy-button-pin { rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; -- 2.25.1