From ba268647368844ed290e2f7b4da7a28cd12ee049 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Thu, 10 Jun 2021 22:11:13 -0700 Subject: [PATCH] cxl/component_regs: Fix offset The CXL.cache and CXL.mem registers begin after the CXL.io registers which occupy the first 0x1000 bytes. The current code wasn't setting this up properly for future users of the component registers. It was correct for the probing code however. Cc: Jonathan Cameron Cc: Ira Weiny Fixes: 08422378c4ad ("cxl/pci: Add HDM decoder capabilities") Signed-off-by: Ben Widawsky Acked-by: Jonathan Cameron Link: https://lore.kernel.org/r/20210611051113.224328-1-ben.widawsky@intel.com Signed-off-by: Dan Williams --- drivers/cxl/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cxl/core.c b/drivers/cxl/core.c index b134b29923ca..c613dc795498 100644 --- a/drivers/cxl/core.c +++ b/drivers/cxl/core.c @@ -599,7 +599,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base, length = 0x20 * decoder_cnt + 0x10; map->hdm_decoder.valid = true; - map->hdm_decoder.offset = offset; + map->hdm_decoder.offset = CXL_CM_OFFSET + offset; map->hdm_decoder.size = length; break; default: -- 2.25.1