From a1fdd107cd0c7cf3a575c994cc2766c67b6689e0 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Fri, 18 Dec 2020 15:02:44 +0300 Subject: [PATCH] usb: chipidea: tegra: Specify TX FIFO threshold in UDC SoC info The UDC/OTG controller could be switched to a host mode and the TXFILLTUNING register needs to be programmed properly for the host mode. Hence specify the TX FIFO threshold in the UDC SoC info. Acked-by: Peter Chen Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201218120246.7759-8-digetx@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/chipidea/ci_hdrc_tegra.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/usb/chipidea/ci_hdrc_tegra.c b/drivers/usb/chipidea/ci_hdrc_tegra.c index 655671159511..90f2a8b786be 100644 --- a/drivers/usb/chipidea/ci_hdrc_tegra.c +++ b/drivers/usb/chipidea/ci_hdrc_tegra.c @@ -52,11 +52,20 @@ static const struct tegra_usb_soc_info tegra30_ehci_soc_info = { .txfifothresh = 16, }; -static const struct tegra_usb_soc_info tegra_udc_soc_info = { +static const struct tegra_usb_soc_info tegra20_udc_soc_info = { .flags = CI_HDRC_REQUIRES_ALIGNED_DMA | CI_HDRC_OVERRIDE_PHY_CONTROL | CI_HDRC_SUPPORTS_RUNTIME_PM, .dr_mode = USB_DR_MODE_UNKNOWN, + .txfifothresh = 10, +}; + +static const struct tegra_usb_soc_info tegra30_udc_soc_info = { + .flags = CI_HDRC_REQUIRES_ALIGNED_DMA | + CI_HDRC_OVERRIDE_PHY_CONTROL | + CI_HDRC_SUPPORTS_RUNTIME_PM, + .dr_mode = USB_DR_MODE_UNKNOWN, + .txfifothresh = 16, }; static const struct of_device_id tegra_usb_of_match[] = { @@ -68,16 +77,16 @@ static const struct of_device_id tegra_usb_of_match[] = { .data = &tegra30_ehci_soc_info, }, { .compatible = "nvidia,tegra20-udc", - .data = &tegra_udc_soc_info, + .data = &tegra20_udc_soc_info, }, { .compatible = "nvidia,tegra30-udc", - .data = &tegra_udc_soc_info, + .data = &tegra30_udc_soc_info, }, { .compatible = "nvidia,tegra114-udc", - .data = &tegra_udc_soc_info, + .data = &tegra30_udc_soc_info, }, { .compatible = "nvidia,tegra124-udc", - .data = &tegra_udc_soc_info, + .data = &tegra30_udc_soc_info, }, { /* sentinel */ } -- 2.25.1