From 9af9fe5bf3e06471666f26fa5dbc271825d04ae4 Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Tue, 28 Apr 2020 16:42:30 +0800 Subject: [PATCH] drm/amd/powerplay: support mclk socclk limit value set for sienna_cichlid. Add support to force and unforce MCLK or SOCCLK to dpm limit value. Signed-off-by: Likun Gao Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c index 667c912e47fd..ef8532ff8e30 100644 --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c @@ -945,6 +945,8 @@ static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool hi enum smu_clk_type clks[] = { SMU_GFXCLK, + SMU_MCLK, + SMU_SOCCLK, }; for (i = 0; i < ARRAY_SIZE(clks); i++) { @@ -970,6 +972,8 @@ static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu) enum smu_clk_type clks[] = { SMU_GFXCLK, + SMU_MCLK, + SMU_SOCCLK, }; for (i = 0; i < ARRAY_SIZE(clks); i++) { -- 2.25.1