From 88347987574b435b23fced20982dc15115ff81b8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 12 May 2024 01:04:10 +0300 Subject: [PATCH] arm64: dts: qcom: sm8250: add a link between DWC3 and QMP PHY The SuperSpeed signals originate from the DWC3 host controller and then are routed through the Combo QMP PHY, where they are multiplexed with the DisplayPort signals. Add corresponding OF graph link. Reported-by: Luca Weiss Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-4-ad153c747a97@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4ec9541ce104..f3f9dea0550b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3951,6 +3951,10 @@ port@1 { reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss_out>; + }; }; port@2 { @@ -4229,8 +4233,24 @@ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_1_dwc3_hs_out: endpoint {}; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; }; }; }; -- 2.25.1