From 60b8d3a2365a30aadd514aaf571c6baecd9885ba Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Mar 2025 19:11:14 +0100 Subject: [PATCH] dt-bindings: display: msm: sm8350-mdss: Describe the CPU-CFG icc path There's a separate path that allows register access from CPUSS. Describe it. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/641464/ Link: https://lore.kernel.org/r/20250306-topic-dt_bindings_fixups-v1-2-0c84aceb0ef9@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml index 163fc83c1e80..3733d8cd2ae0 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml @@ -38,12 +38,16 @@ properties: maxItems: 1 interconnects: - maxItems: 2 + items: + - description: Interconnect path from the MDP0 port to the data bus + - description: Interconnect path from the MDP1 port to the data bus + - description: Interconnect path from the CPU to the reg bus interconnect-names: items: - const: mdp0-mem - const: mdp1-mem + - const: cpu-cfg patternProperties: "^display-controller@[0-9a-f]+$": -- 2.25.1