From 331bbcfc50aa45ca744f35109de7297deaa6356f Mon Sep 17 00:00:00 2001 From: =?utf8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 7 May 2018 11:27:03 +0200 Subject: [PATCH] spi: remove the older/duplicated bcm53xx driver MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This driver was added by commit 0fc6a323e1917 ("spi: bcm53xx: driver for SPI controller on Broadcom bcma SoC") back in 2014. It was needed to provide a minimal support for SPI controller on BCM5301X (AKA Northstar) devices. An alternative driver was added by Kamal in commit fa236a7ef2404 ("spi: bcm-qspi: Add Broadcom MSPI driver") 2 years later. It supports the same hardware but for some reason a new driver has been developed for it. At this point the new driver supports: more modes, setting a speed, setting bits per word and uses IRQs instead of polling. DTS file for BCM5301X has also been updated in the commit 1c8f406507238 ("ARM: dts: BCM5301X: convert to iProc QSPI") - over a year ago. That explained I see no reason to keep the old driver alive. Signed-off-by: Rafał Miłecki Signed-off-by: Mark Brown --- drivers/spi/spi-bcm53xx.c | 360 -------------------------------------- drivers/spi/spi-bcm53xx.h | 73 -------- 2 files changed, 433 deletions(-) delete mode 100644 drivers/spi/spi-bcm53xx.c delete mode 100644 drivers/spi/spi-bcm53xx.h diff --git a/drivers/spi/spi-bcm53xx.c b/drivers/spi/spi-bcm53xx.c deleted file mode 100644 index d02ceb7a29d1..000000000000 --- a/drivers/spi/spi-bcm53xx.c +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Copyright (C) 2014-2016 Rafał Miłecki - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include - -#include "spi-bcm53xx.h" - -#define BCM53XXSPI_MAX_SPI_BAUD 13500000 /* 216 MHz? */ -#define BCM53XXSPI_FLASH_WINDOW SZ_32M - -/* The longest observed required wait was 19 ms */ -#define BCM53XXSPI_SPE_TIMEOUT_MS 80 - -struct bcm53xxspi { - struct bcma_device *core; - struct spi_master *master; - void __iomem *mmio_base; - bool bspi; /* Boot SPI mode with memory mapping */ -}; - -static inline u32 bcm53xxspi_read(struct bcm53xxspi *b53spi, u16 offset) -{ - return bcma_read32(b53spi->core, offset); -} - -static inline void bcm53xxspi_write(struct bcm53xxspi *b53spi, u16 offset, - u32 value) -{ - bcma_write32(b53spi->core, offset, value); -} - -static void bcm53xxspi_disable_bspi(struct bcm53xxspi *b53spi) -{ - struct device *dev = &b53spi->core->dev; - unsigned long deadline; - u32 tmp; - - if (!b53spi->bspi) - return; - - tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL); - if (tmp & 0x1) - return; - - deadline = jiffies + usecs_to_jiffies(200); - do { - tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_BUSY_STATUS); - if (!(tmp & 0x1)) { - bcm53xxspi_write(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL, - 0x1); - ndelay(200); - b53spi->bspi = false; - return; - } - udelay(1); - } while (!time_after_eq(jiffies, deadline)); - - dev_warn(dev, "Timeout disabling BSPI\n"); -} - -static void bcm53xxspi_enable_bspi(struct bcm53xxspi *b53spi) -{ - u32 tmp; - - if (b53spi->bspi) - return; - - tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL); - if (!(tmp & 0x1)) - return; - - bcm53xxspi_write(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL, 0x0); - b53spi->bspi = true; -} - -static inline unsigned int bcm53xxspi_calc_timeout(size_t len) -{ - /* Do some magic calculation based on length and buad. Add 10% and 1. */ - return (len * 9000 / BCM53XXSPI_MAX_SPI_BAUD * 110 / 100) + 1; -} - -static int bcm53xxspi_wait(struct bcm53xxspi *b53spi, unsigned int timeout_ms) -{ - unsigned long deadline; - u32 tmp; - - /* SPE bit has to be 0 before we read MSPI STATUS */ - deadline = jiffies + msecs_to_jiffies(BCM53XXSPI_SPE_TIMEOUT_MS); - do { - tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2); - if (!(tmp & B53SPI_MSPI_SPCR2_SPE)) - break; - udelay(5); - } while (!time_after_eq(jiffies, deadline)); - - if (tmp & B53SPI_MSPI_SPCR2_SPE) - goto spi_timeout; - - /* Check status */ - deadline = jiffies + msecs_to_jiffies(timeout_ms); - do { - tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_MSPI_STATUS); - if (tmp & B53SPI_MSPI_MSPI_STATUS_SPIF) { - bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0); - return 0; - } - - cpu_relax(); - udelay(100); - } while (!time_after_eq(jiffies, deadline)); - -spi_timeout: - bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0); - - pr_err("Timeout waiting for SPI to be ready!\n"); - - return -EBUSY; -} - -static void bcm53xxspi_buf_write(struct bcm53xxspi *b53spi, u8 *w_buf, - size_t len, bool cont) -{ - u32 tmp; - int i; - - for (i = 0; i < len; i++) { - /* Transmit Register File MSB */ - bcm53xxspi_write(b53spi, B53SPI_MSPI_TXRAM + 4 * (i * 2), - (unsigned int)w_buf[i]); - } - - for (i = 0; i < len; i++) { - tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL | - B53SPI_CDRAM_PCS_DSCK; - if (!cont && i == len - 1) - tmp &= ~B53SPI_CDRAM_CONT; - tmp &= ~0x1; - /* Command Register File */ - bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp); - } - - /* Set queue pointers */ - bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0); - bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP, len - 1); - - if (cont) - bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1); - - /* Start SPI transfer */ - tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2); - tmp |= B53SPI_MSPI_SPCR2_SPE; - if (cont) - tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD; - bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp); - - /* Wait for SPI to finish */ - bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len)); - - if (!cont) - bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0); -} - -static void bcm53xxspi_buf_read(struct bcm53xxspi *b53spi, u8 *r_buf, - size_t len, bool cont) -{ - u32 tmp; - int i; - - for (i = 0; i < len; i++) { - tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL | - B53SPI_CDRAM_PCS_DSCK; - if (!cont && i == len - 1) - tmp &= ~B53SPI_CDRAM_CONT; - tmp &= ~0x1; - /* Command Register File */ - bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp); - } - - /* Set queue pointers */ - bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0); - bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP, len - 1); - - if (cont) - bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1); - - /* Start SPI transfer */ - tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2); - tmp |= B53SPI_MSPI_SPCR2_SPE; - if (cont) - tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD; - bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp); - - /* Wait for SPI to finish */ - bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len)); - - if (!cont) - bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0); - - for (i = 0; i < len; ++i) { - u16 reg = B53SPI_MSPI_RXRAM + 4 * (1 + i * 2); - - /* Data stored in the transmit register file LSB */ - r_buf[i] = (u8)bcm53xxspi_read(b53spi, reg); - } -} - -static int bcm53xxspi_transfer_one(struct spi_master *master, - struct spi_device *spi, - struct spi_transfer *t) -{ - struct bcm53xxspi *b53spi = spi_master_get_devdata(master); - u8 *buf; - size_t left; - - bcm53xxspi_disable_bspi(b53spi); - - if (t->tx_buf) { - buf = (u8 *)t->tx_buf; - left = t->len; - while (left) { - size_t to_write = min_t(size_t, 16, left); - bool cont = !spi_transfer_is_last(master, t) || - left - to_write > 0; - - bcm53xxspi_buf_write(b53spi, buf, to_write, cont); - left -= to_write; - buf += to_write; - } - } - - if (t->rx_buf) { - buf = (u8 *)t->rx_buf; - left = t->len; - while (left) { - size_t to_read = min_t(size_t, 16, left); - bool cont = !spi_transfer_is_last(master, t) || - left - to_read > 0; - - bcm53xxspi_buf_read(b53spi, buf, to_read, cont); - left -= to_read; - buf += to_read; - } - } - - return 0; -} - -static int bcm53xxspi_flash_read(struct spi_device *spi, - struct spi_flash_read_message *msg) -{ - struct bcm53xxspi *b53spi = spi_master_get_devdata(spi->master); - int ret = 0; - - if (msg->from + msg->len > BCM53XXSPI_FLASH_WINDOW) - return -EINVAL; - - bcm53xxspi_enable_bspi(b53spi); - memcpy_fromio(msg->buf, b53spi->mmio_base + msg->from, msg->len); - msg->retlen = msg->len; - - return ret; -} - -/************************************************** - * BCMA - **************************************************/ - -static const struct bcma_device_id bcm53xxspi_bcma_tbl[] = { - BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_QSPI, BCMA_ANY_REV, BCMA_ANY_CLASS), - {}, -}; -MODULE_DEVICE_TABLE(bcma, bcm53xxspi_bcma_tbl); - -static int bcm53xxspi_bcma_probe(struct bcma_device *core) -{ - struct device *dev = &core->dev; - struct bcm53xxspi *b53spi; - struct spi_master *master; - int err; - - if (core->bus->drv_cc.core->id.rev != 42) { - pr_err("SPI on SoC with unsupported ChipCommon rev\n"); - return -ENOTSUPP; - } - - master = spi_alloc_master(dev, sizeof(*b53spi)); - if (!master) - return -ENOMEM; - - b53spi = spi_master_get_devdata(master); - b53spi->master = master; - b53spi->core = core; - - if (core->addr_s[0]) - b53spi->mmio_base = devm_ioremap(dev, core->addr_s[0], - BCM53XXSPI_FLASH_WINDOW); - b53spi->bspi = true; - bcm53xxspi_disable_bspi(b53spi); - - master->dev.of_node = dev->of_node; - master->transfer_one = bcm53xxspi_transfer_one; - if (b53spi->mmio_base) - master->spi_flash_read = bcm53xxspi_flash_read; - - bcma_set_drvdata(core, b53spi); - - err = devm_spi_register_master(dev, master); - if (err) { - spi_master_put(master); - bcma_set_drvdata(core, NULL); - return err; - } - - return 0; -} - -static struct bcma_driver bcm53xxspi_bcma_driver = { - .name = KBUILD_MODNAME, - .id_table = bcm53xxspi_bcma_tbl, - .probe = bcm53xxspi_bcma_probe, -}; - -/************************************************** - * Init & exit - **************************************************/ - -static int __init bcm53xxspi_module_init(void) -{ - int err = 0; - - err = bcma_driver_register(&bcm53xxspi_bcma_driver); - if (err) - pr_err("Failed to register bcma driver: %d\n", err); - - return err; -} - -static void __exit bcm53xxspi_module_exit(void) -{ - bcma_driver_unregister(&bcm53xxspi_bcma_driver); -} - -module_init(bcm53xxspi_module_init); -module_exit(bcm53xxspi_module_exit); - -MODULE_DESCRIPTION("Broadcom BCM53xx SPI Controller driver"); -MODULE_AUTHOR("Rafał Miłecki "); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/spi/spi-bcm53xx.h b/drivers/spi/spi-bcm53xx.h deleted file mode 100644 index 03e3442086ec..000000000000 --- a/drivers/spi/spi-bcm53xx.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef SPI_BCM53XX_H -#define SPI_BCM53XX_H - -#define B53SPI_BSPI_REVISION_ID 0x000 -#define B53SPI_BSPI_SCRATCH 0x004 -#define B53SPI_BSPI_MAST_N_BOOT_CTRL 0x008 -#define B53SPI_BSPI_BUSY_STATUS 0x00c -#define B53SPI_BSPI_INTR_STATUS 0x010 -#define B53SPI_BSPI_B0_STATUS 0x014 -#define B53SPI_BSPI_B0_CTRL 0x018 -#define B53SPI_BSPI_B1_STATUS 0x01c -#define B53SPI_BSPI_B1_CTRL 0x020 -#define B53SPI_BSPI_STRAP_OVERRIDE_CTRL 0x024 -#define B53SPI_BSPI_FLEX_MODE_ENABLE 0x028 -#define B53SPI_BSPI_BITS_PER_CYCLE 0x02c -#define B53SPI_BSPI_BITS_PER_PHASE 0x030 -#define B53SPI_BSPI_CMD_AND_MODE_BYTE 0x034 -#define B53SPI_BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038 -#define B53SPI_BSPI_BSPI_XOR_VALUE 0x03c -#define B53SPI_BSPI_BSPI_XOR_ENABLE 0x040 -#define B53SPI_BSPI_BSPI_PIO_MODE_ENABLE 0x044 -#define B53SPI_BSPI_BSPI_PIO_IODIR 0x048 -#define B53SPI_BSPI_BSPI_PIO_DATA 0x04c - -/* RAF */ -#define B53SPI_RAF_START_ADDR 0x100 -#define B53SPI_RAF_NUM_WORDS 0x104 -#define B53SPI_RAF_CTRL 0x108 -#define B53SPI_RAF_FULLNESS 0x10c -#define B53SPI_RAF_WATERMARK 0x110 -#define B53SPI_RAF_STATUS 0x114 -#define B53SPI_RAF_READ_DATA 0x118 -#define B53SPI_RAF_WORD_CNT 0x11c -#define B53SPI_RAF_CURR_ADDR 0x120 - -/* MSPI */ -#define B53SPI_MSPI_SPCR0_LSB 0x200 -#define B53SPI_MSPI_SPCR0_MSB 0x204 -#define B53SPI_MSPI_SPCR1_LSB 0x208 -#define B53SPI_MSPI_SPCR1_MSB 0x20c -#define B53SPI_MSPI_NEWQP 0x210 -#define B53SPI_MSPI_ENDQP 0x214 -#define B53SPI_MSPI_SPCR2 0x218 -#define B53SPI_MSPI_SPCR2_SPE 0x00000040 -#define B53SPI_MSPI_SPCR2_CONT_AFTER_CMD 0x00000080 -#define B53SPI_MSPI_MSPI_STATUS 0x220 -#define B53SPI_MSPI_MSPI_STATUS_SPIF 0x00000001 -#define B53SPI_MSPI_CPTQP 0x224 -#define B53SPI_MSPI_TXRAM 0x240 /* 32 registers, up to 0x2b8 */ -#define B53SPI_MSPI_RXRAM 0x2c0 /* 32 registers, up to 0x33c */ -#define B53SPI_MSPI_CDRAM 0x340 /* 16 registers, up to 0x37c */ -#define B53SPI_CDRAM_PCS_PCS0 0x00000001 -#define B53SPI_CDRAM_PCS_PCS1 0x00000002 -#define B53SPI_CDRAM_PCS_PCS2 0x00000004 -#define B53SPI_CDRAM_PCS_PCS3 0x00000008 -#define B53SPI_CDRAM_PCS_DISABLE_ALL 0x0000000f -#define B53SPI_CDRAM_PCS_DSCK 0x00000010 -#define B53SPI_CDRAM_BITSE 0x00000040 -#define B53SPI_CDRAM_CONT 0x00000080 -#define B53SPI_MSPI_WRITE_LOCK 0x380 -#define B53SPI_MSPI_DISABLE_FLUSH_GEN 0x384 - -/* Interrupt */ -#define B53SPI_INTR_RAF_LR_FULLNESS_REACHED 0x3a0 -#define B53SPI_INTR_RAF_LR_TRUNCATED 0x3a4 -#define B53SPI_INTR_RAF_LR_IMPATIENT 0x3a8 -#define B53SPI_INTR_RAF_LR_SESSION_DONE 0x3ac -#define B53SPI_INTR_RAF_LR_OVERREAD 0x3b0 -#define B53SPI_INTR_MSPI_DONE 0x3b4 -#define B53SPI_INTR_MSPI_HALT_SET_TRANSACTION_DONE 0x3b8 - -#endif /* SPI_BCM53XX_H */ -- 2.25.1