From 2d6c7bcc6cca63238fce0a95874b053500a1112e Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 7 Apr 2025 12:17:04 +0200 Subject: [PATCH] scsi: ufs: core: Track when MCQ ESI is enabled In preparation of adding a threaded interrupt handler, track when the MCQ ESI interrupt handlers were installed so we can optimize the MCQ interrupt handling to avoid walking the threaded handler in the case ESI handlers are enabled. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250407-topic-ufs-use-threaded-irq-v3-2-08bee980f71e@linaro.org Reviewed-by: Bart Van Assche Signed-off-by: Martin K. Petersen --- drivers/ufs/core/ufshcd.c | 1 + include/ufs/ufshcd.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 5e73ac1e0078..7f256f77b8ba 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -8717,6 +8717,7 @@ static void ufshcd_config_mcq(struct ufs_hba *hba) u32 intrs; ret = ufshcd_mcq_vops_config_esi(hba); + hba->mcq_esi_enabled = !ret; dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); intrs = UFSHCD_ENABLE_MCQ_INTRS; diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index fffa9cc46543..ec999fa67124 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -954,6 +954,7 @@ enum ufshcd_mcq_opr { * ufshcd_resume_complete() * @mcq_sup: is mcq supported by UFSHC * @mcq_enabled: is mcq ready to accept requests + * @mcq_esi_enabled: is mcq ESI configured * @res: array of resource info of MCQ registers * @mcq_base: Multi circular queue registers base address * @uhq: array of supported hardware queues @@ -1122,6 +1123,7 @@ struct ufs_hba { bool mcq_sup; bool lsdb_sup; bool mcq_enabled; + bool mcq_esi_enabled; struct ufshcd_res_info res[RES_MAX]; void __iomem *mcq_base; struct ufs_hw_queue *uhq; -- 2.25.1