From 28aa30b08de6f4b346f25f7c8bb5ba3739c1879c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 12 Jan 2022 09:40:34 +0100 Subject: [PATCH] drm/tegra: Fix planar formats on Tegra186 and later Use the correct pitch when programming the DC_WIN_PLANAR_STORAGE_UV register's PITCH_U field to ensure the correct value is used in all cases. This isn't currently causing any problems because the pitch for both U and V planes is always the same. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/hub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c index b910155f80c4..fc9813e6b2c9 100644 --- a/drivers/gpu/drm/tegra/hub.c +++ b/drivers/gpu/drm/tegra/hub.c @@ -673,7 +673,7 @@ static void tegra_shared_plane_atomic_update(struct drm_plane *plane, tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V); tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V); - value = PITCH_U(fb->pitches[2]) | PITCH_V(fb->pitches[2]); + value = PITCH_U(fb->pitches[1]) | PITCH_V(fb->pitches[2]); tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV); } else { tegra_plane_writel(p, 0, DC_WINBUF_START_ADDR_U); -- 2.25.1