From 1cbb91cb29a71f0a22f6909bf9c0ad43bd315bae Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Fri, 26 Apr 2024 11:25:50 -0600 Subject: [PATCH] drm/amd/display: Limit clock assignments by size of clk tables [WHAT & HOW] Check clk table's array size to avoid out-of-bound memory accesses. This fixes two OVERRUN issues reported by Coverity. Reviewed-by: Harry Wentland Acked-by: Tom Chung Signed-off-by: Alex Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c index 005092b0a0cb..7db7446ad91f 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c @@ -130,7 +130,7 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c *num_levels = ret & 0xFF; /* if the initial message failed, num_levels will be 0 */ - for (i = 0; i < *num_levels; i++) { + for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) { *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF); entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); } -- 2.25.1