From 0fac5141d646638d64851cea4f493204faee1282 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 18 Feb 2025 20:11:55 +1000 Subject: [PATCH] drm/nouveau/gsp: add display class ids to gpu hal Use display class IDs from nvkm_rm_gpu, instead of copying them from the non-GSP HALs. Removes the AD102 display HAL, which is no longer required as there's no support for it without GSP-RM. Signed-off-by: Ben Skeggs Reviewed-by: Dave Airlie Reviewed-by: Timur Tabi Tested-by: Timur Tabi Signed-off-by: Dave Airlie --- .../drm/nouveau/include/nvkm/engine/disp.h | 1 - .../gpu/drm/nouveau/nvkm/engine/device/base.c | 10 ++-- .../gpu/drm/nouveau/nvkm/engine/disp/Kbuild | 1 - .../gpu/drm/nouveau/nvkm/engine/disp/ad102.c | 52 ------------------- .../drm/nouveau/nvkm/subdev/gsp/rm/ad10x.c | 10 ++++ .../drm/nouveau/nvkm/subdev/gsp/rm/ga1xx.c | 10 ++++ .../gpu/drm/nouveau/nvkm/subdev/gsp/rm/gpu.h | 10 ++++ .../nouveau/nvkm/subdev/gsp/rm/r535/disp.c | 35 ++++++++----- .../drm/nouveau/nvkm/subdev/gsp/rm/tu1xx.c | 10 ++++ 9 files changed, 67 insertions(+), 72 deletions(-) delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/disp/ad102.c diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h index 3e8db8280e2a..7903d7470d19 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h @@ -87,5 +87,4 @@ int gp102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct int gv100_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); int tu102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); int ga102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); -int ad102_disp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_disp **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 9093d89b16f3..aa929d3b2941 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2709,7 +2709,7 @@ nv192_chipset = { .timer = { 0x00000001, gk20a_timer_new }, .vfn = { 0x00000001, ga100_vfn_new }, .ce = { 0x0000001f, ga102_ce_new }, - .disp = { 0x00000001, ad102_disp_new }, + .disp = { 0x00000001, ga102_disp_new }, .dma = { 0x00000001, gv100_dma_new }, .fifo = { 0x00000001, ga102_fifo_new }, .gr = { 0x00000001, ad102_gr_new }, @@ -2735,7 +2735,7 @@ nv193_chipset = { .timer = { 0x00000001, gk20a_timer_new }, .vfn = { 0x00000001, ga100_vfn_new }, .ce = { 0x0000001f, ga102_ce_new }, - .disp = { 0x00000001, ad102_disp_new }, + .disp = { 0x00000001, ga102_disp_new }, .dma = { 0x00000001, gv100_dma_new }, .fifo = { 0x00000001, ga102_fifo_new }, .gr = { 0x00000001, ad102_gr_new }, @@ -2761,7 +2761,7 @@ nv194_chipset = { .timer = { 0x00000001, gk20a_timer_new }, .vfn = { 0x00000001, ga100_vfn_new }, .ce = { 0x0000001f, ga102_ce_new }, - .disp = { 0x00000001, ad102_disp_new }, + .disp = { 0x00000001, ga102_disp_new }, .dma = { 0x00000001, gv100_dma_new }, .fifo = { 0x00000001, ga102_fifo_new }, .gr = { 0x00000001, ad102_gr_new }, @@ -2787,7 +2787,7 @@ nv196_chipset = { .timer = { 0x00000001, gk20a_timer_new }, .vfn = { 0x00000001, ga100_vfn_new }, .ce = { 0x0000001f, ga102_ce_new }, - .disp = { 0x00000001, ad102_disp_new }, + .disp = { 0x00000001, ga102_disp_new }, .dma = { 0x00000001, gv100_dma_new }, .fifo = { 0x00000001, ga102_fifo_new }, .gr = { 0x00000001, ad102_gr_new }, @@ -2813,7 +2813,7 @@ nv197_chipset = { .timer = { 0x00000001, gk20a_timer_new }, .vfn = { 0x00000001, ga100_vfn_new }, .ce = { 0x0000001f, ga102_ce_new }, - .disp = { 0x00000001, ad102_disp_new }, + .disp = { 0x00000001, ga102_disp_new }, .dma = { 0x00000001, gv100_dma_new }, .fifo = { 0x00000001, ga102_fifo_new }, .gr = { 0x00000001, ad102_gr_new }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild index 23a10e081081..e1aecd3fe96c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild @@ -27,7 +27,6 @@ nvkm-y += nvkm/engine/disp/gp102.o nvkm-y += nvkm/engine/disp/gv100.o nvkm-y += nvkm/engine/disp/tu102.o nvkm-y += nvkm/engine/disp/ga102.o -nvkm-y += nvkm/engine/disp/ad102.o nvkm-y += nvkm/engine/disp/udisp.o nvkm-y += nvkm/engine/disp/uconn.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ad102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ad102.c deleted file mode 100644 index 7f300a79aa29..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ad102.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright 2023 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "priv.h" -#include "chan.h" - -#include - -#include - -static const struct nvkm_disp_func -ad102_disp = { - .uevent = &gv100_disp_chan_uevent, - .ramht_size = 0x2000, - .root = { 0, 0,AD102_DISP }, - .user = { - {{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new }, - {{ 0, 0,GA102_DISP_CURSOR }, nvkm_disp_chan_new, &gv100_disp_curs }, - {{ 0, 0,GA102_DISP_WINDOW_IMM_CHANNEL_DMA}, nvkm_disp_wndw_new, &gv100_disp_wimm }, - {{ 0, 0,AD102_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, &gv100_disp_core }, - {{ 0, 0,GA102_DISP_WINDOW_CHANNEL_DMA }, nvkm_disp_wndw_new, &gv100_disp_wndw }, - {} - }, -}; - -int -ad102_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, - struct nvkm_disp **pdisp) -{ - if (nvkm_gsp_rm(device->gsp)) - return r535_disp_new(&ad102_disp, device, type, inst, pdisp); - - return -ENODEV; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ad10x.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ad10x.c index 1e519bf166dd..bdeaffbb1077 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ad10x.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ad10x.c @@ -4,6 +4,16 @@ */ #include "gpu.h" +#include + const struct nvkm_rm_gpu ad10x_gpu = { + .disp.class = { + .root = AD102_DISP, + .caps = GV100_DISP_CAPS, + .core = AD102_DISP_CORE_CHANNEL_DMA, + .wndw = GA102_DISP_WINDOW_CHANNEL_DMA, + .wimm = GA102_DISP_WINDOW_IMM_CHANNEL_DMA, + .curs = GA102_DISP_CURSOR, + }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ga1xx.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ga1xx.c index 725ccb2c27dc..d4b67ccac608 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ga1xx.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ga1xx.c @@ -4,6 +4,16 @@ */ #include "gpu.h" +#include + const struct nvkm_rm_gpu ga1xx_gpu = { + .disp.class = { + .root = GA102_DISP, + .caps = GV100_DISP_CAPS, + .core = GA102_DISP_CORE_CHANNEL_DMA, + .wndw = GA102_DISP_WINDOW_CHANNEL_DMA, + .wimm = GA102_DISP_WINDOW_IMM_CHANNEL_DMA, + .curs = GA102_DISP_CURSOR, + }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gpu.h b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gpu.h index 32d87ce2b77d..7f3b5f3fd32b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gpu.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gpu.h @@ -7,6 +7,16 @@ #include "rm.h" struct nvkm_rm_gpu { + struct { + struct { + u32 root; + u32 caps; + u32 core; + u32 wndw; + u32 wimm; + u32 curs; + } class; + } disp; }; extern const struct nvkm_rm_gpu tu1xx_gpu; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c index 475faa35361a..e65f9074e94f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c @@ -34,6 +34,8 @@ #include #include +#include + #include #include "nvrm/disp.h" @@ -1676,6 +1678,7 @@ int r535_disp_new(const struct nvkm_disp_func *hw, struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_disp **pdisp) { + const struct nvkm_rm_gpu *gpu = device->gsp->rm->gpu; struct nvkm_disp_func *rm; int ret; @@ -1691,20 +1694,26 @@ r535_disp_new(const struct nvkm_disp_func *hw, struct nvkm_device *device, rm->sor.new = r535_sor_new; rm->ramht_size = hw->ramht_size; - rm->root = hw->root; + rm->root.oclass = gpu->disp.class.root; - for (int i = 0; hw->user[i].ctor; i++) { - switch (hw->user[i].base.oclass & 0xff) { - case 0x73: rm->user[i] = hw->user[i]; break; - case 0x7d: rm->user[i] = hw->user[i]; rm->user[i].chan = &r535_core; break; - case 0x7e: rm->user[i] = hw->user[i]; rm->user[i].chan = &r535_wndw; break; - case 0x7b: rm->user[i] = hw->user[i]; rm->user[i].chan = &r535_wimm; break; - case 0x7a: rm->user[i] = hw->user[i]; rm->user[i].chan = &r535_curs; break; - default: - WARN_ON(1); - continue; - } - } + rm->user[0].base.oclass = gpu->disp.class.caps; + rm->user[0].ctor = gv100_disp_caps_new; + + rm->user[1].base.oclass = gpu->disp.class.core; + rm->user[1].ctor = nvkm_disp_core_new; + rm->user[1].chan = &r535_core; + + rm->user[2].base.oclass = gpu->disp.class.wndw; + rm->user[2].ctor = nvkm_disp_wndw_new; + rm->user[2].chan = &r535_wndw; + + rm->user[3].base.oclass = gpu->disp.class.wimm; + rm->user[3].ctor = nvkm_disp_wndw_new; + rm->user[3].chan = &r535_wimm; + + rm->user[4].base.oclass = gpu->disp.class.curs; + rm->user[4].ctor = nvkm_disp_chan_new; + rm->user[4].chan = &r535_curs; ret = nvkm_disp_new_(rm, device, type, inst, pdisp); if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/tu1xx.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/tu1xx.c index d455a4f19854..add98b2f3b6d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/tu1xx.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/tu1xx.c @@ -4,6 +4,16 @@ */ #include "gpu.h" +#include + const struct nvkm_rm_gpu tu1xx_gpu = { + .disp.class = { + .root = TU102_DISP, + .caps = GV100_DISP_CAPS, + .core = TU102_DISP_CORE_CHANNEL_DMA, + .wndw = TU102_DISP_WINDOW_CHANNEL_DMA, + .wimm = TU102_DISP_WINDOW_IMM_CHANNEL_DMA, + .curs = TU102_DISP_CURSOR, + }, }; -- 2.25.1