From 06e3c7ec804524767f529404d023993fbca9ea43 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Wed, 30 Oct 2024 18:38:39 +0530 Subject: [PATCH] arm64: dts: qcom: x1e80100: Add cpucp mailbox and sram nodes Add the cpucp mailbox and sram nodes required by SCMI perf protocol on X1E80100 SoCs. Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/20241030130840.2890904-2-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 06175b33bd92..05d8d9643f61 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -7980,6 +7980,13 @@ }; }; + cpucp_mbox: mailbox@17430000 { + compatible = "qcom,x1e80100-cpucp-mbox"; + reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>; + interrupts = ; + #mbox-cells = <1>; + }; + apps_rsc: rsc@17500000 { compatible = "qcom,rpmh-rsc"; reg = <0 0x17500000 0 0x10000>, @@ -8163,6 +8170,25 @@ }; }; + sram: sram@18b4e000 { + compatible = "mmio-sram"; + reg = <0x0 0x18b4e000 0x0 0x400>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x18b4e000 0x400>; + + cpu_scp_lpri0: scp-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x200>; + }; + + cpu_scp_lpri1: scp-sram-section@200 { + compatible = "arm,scmi-shmem"; + reg = <0x200 0x200>; + }; + }; + sbsa_watchdog: watchdog@1c840000 { compatible = "arm,sbsa-gwdt"; reg = <0 0x1c840000 0 0x1000>, -- 2.25.1