From 02e2224796a3b609d47bc3a1b78cc833289d7d1f Mon Sep 17 00:00:00 2001 From: Gustavo Sousa Date: Fri, 8 Nov 2024 09:57:15 -0300 Subject: [PATCH] drm/i915/dmc_wl: Allow simpler syntax for single reg in range tables Allow simpler syntax for defining entries for single registers in range tables. That makes them easier to type as well as to read, allowing one to quickly tell whether a range actually refers to a single register or a "true range". Reviewed-by: Luca Coelho Signed-off-by: Gustavo Sousa Signed-off-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20241108130218.24125-11-gustavo.sousa@intel.com --- drivers/gpu/drm/i915/display/intel_dmc_wl.c | 118 ++++++++++---------- 1 file changed, 60 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index db01b65cb05d..4a182a049374 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -58,82 +58,82 @@ static struct intel_dmc_wl_range powered_off_ranges[] = { }; static struct intel_dmc_wl_range xe3lpd_dc5_dc6_dmc_ranges[] = { - { .start = 0x45500, .end = 0x45500 }, /* DC_STATE_SEL */ + { .start = 0x45500 }, /* DC_STATE_SEL */ { .start = 0x457a0, .end = 0x457b0 }, /* DC*_RESIDENCY_COUNTER */ - { .start = 0x45504, .end = 0x45504 }, /* DC_STATE_EN */ + { .start = 0x45504 }, /* DC_STATE_EN */ { .start = 0x45400, .end = 0x4540c }, /* PWR_WELL_CTL_* */ - { .start = 0x454f0, .end = 0x454f0 }, /* RETENTION_CTRL */ + { .start = 0x454f0 }, /* RETENTION_CTRL */ /* DBUF_CTL_* */ - { .start = 0x44300, .end = 0x44300 }, - { .start = 0x44304, .end = 0x44304 }, - { .start = 0x44f00, .end = 0x44f00 }, - { .start = 0x44f04, .end = 0x44f04 }, - { .start = 0x44fe8, .end = 0x44fe8 }, - { .start = 0x45008, .end = 0x45008 }, + { .start = 0x44300 }, + { .start = 0x44304 }, + { .start = 0x44f00 }, + { .start = 0x44f04 }, + { .start = 0x44fe8 }, + { .start = 0x45008 }, - { .start = 0x46070, .end = 0x46070 }, /* CDCLK_PLL_ENABLE */ - { .start = 0x46000, .end = 0x46000 }, /* CDCLK_CTL */ - { .start = 0x46008, .end = 0x46008 }, /* CDCLK_SQUASH_CTL */ + { .start = 0x46070 }, /* CDCLK_PLL_ENABLE */ + { .start = 0x46000 }, /* CDCLK_CTL */ + { .start = 0x46008 }, /* CDCLK_SQUASH_CTL */ /* TRANS_CMTG_CTL_* */ - { .start = 0x6fa88, .end = 0x6fa88 }, - { .start = 0x6fb88, .end = 0x6fb88 }, - - { .start = 0x46430, .end = 0x46430 }, /* CHICKEN_DCPR_1 */ - { .start = 0x46434, .end = 0x46434 }, /* CHICKEN_DCPR_2 */ - { .start = 0x454a0, .end = 0x454a0 }, /* CHICKEN_DCPR_4 */ - { .start = 0x42084, .end = 0x42084 }, /* CHICKEN_MISC_2 */ - { .start = 0x42088, .end = 0x42088 }, /* CHICKEN_MISC_3 */ - { .start = 0x46160, .end = 0x46160 }, /* CMTG_CLK_SEL */ + { .start = 0x6fa88 }, + { .start = 0x6fb88 }, + + { .start = 0x46430 }, /* CHICKEN_DCPR_1 */ + { .start = 0x46434 }, /* CHICKEN_DCPR_2 */ + { .start = 0x454a0 }, /* CHICKEN_DCPR_4 */ + { .start = 0x42084 }, /* CHICKEN_MISC_2 */ + { .start = 0x42088 }, /* CHICKEN_MISC_3 */ + { .start = 0x46160 }, /* CMTG_CLK_SEL */ { .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */ {}, }; static struct intel_dmc_wl_range xe3lpd_dc3co_dmc_ranges[] = { - { .start = 0x454a0, .end = 0x454a0 }, /* CHICKEN_DCPR_4 */ + { .start = 0x454a0 }, /* CHICKEN_DCPR_4 */ - { .start = 0x45504, .end = 0x45504 }, /* DC_STATE_EN */ + { .start = 0x45504 }, /* DC_STATE_EN */ /* DBUF_CTL_* */ - { .start = 0x44300, .end = 0x44300 }, - { .start = 0x44304, .end = 0x44304 }, - { .start = 0x44f00, .end = 0x44f00 }, - { .start = 0x44f04, .end = 0x44f04 }, - { .start = 0x44fe8, .end = 0x44fe8 }, - { .start = 0x45008, .end = 0x45008 }, - - { .start = 0x46070, .end = 0x46070 }, /* CDCLK_PLL_ENABLE */ - { .start = 0x46000, .end = 0x46000 }, /* CDCLK_CTL */ - { .start = 0x46008, .end = 0x46008 }, /* CDCLK_SQUASH_CTL */ + { .start = 0x44300 }, + { .start = 0x44304 }, + { .start = 0x44f00 }, + { .start = 0x44f04 }, + { .start = 0x44fe8 }, + { .start = 0x45008 }, + + { .start = 0x46070 }, /* CDCLK_PLL_ENABLE */ + { .start = 0x46000 }, /* CDCLK_CTL */ + { .start = 0x46008 }, /* CDCLK_SQUASH_CTL */ { .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */ /* Scanline registers */ - { .start = 0x70000, .end = 0x70000 }, - { .start = 0x70004, .end = 0x70004 }, - { .start = 0x70014, .end = 0x70014 }, - { .start = 0x70018, .end = 0x70018 }, - { .start = 0x71000, .end = 0x71000 }, - { .start = 0x71004, .end = 0x71004 }, - { .start = 0x71014, .end = 0x71014 }, - { .start = 0x71018, .end = 0x71018 }, - { .start = 0x72000, .end = 0x72000 }, - { .start = 0x72004, .end = 0x72004 }, - { .start = 0x72014, .end = 0x72014 }, - { .start = 0x72018, .end = 0x72018 }, - { .start = 0x73000, .end = 0x73000 }, - { .start = 0x73004, .end = 0x73004 }, - { .start = 0x73014, .end = 0x73014 }, - { .start = 0x73018, .end = 0x73018 }, - { .start = 0x7b000, .end = 0x7b000 }, - { .start = 0x7b004, .end = 0x7b004 }, - { .start = 0x7b014, .end = 0x7b014 }, - { .start = 0x7b018, .end = 0x7b018 }, - { .start = 0x7c000, .end = 0x7c000 }, - { .start = 0x7c004, .end = 0x7c004 }, - { .start = 0x7c014, .end = 0x7c014 }, - { .start = 0x7c018, .end = 0x7c018 }, + { .start = 0x70000 }, + { .start = 0x70004 }, + { .start = 0x70014 }, + { .start = 0x70018 }, + { .start = 0x71000 }, + { .start = 0x71004 }, + { .start = 0x71014 }, + { .start = 0x71018 }, + { .start = 0x72000 }, + { .start = 0x72004 }, + { .start = 0x72014 }, + { .start = 0x72018 }, + { .start = 0x73000 }, + { .start = 0x73004 }, + { .start = 0x73014 }, + { .start = 0x73018 }, + { .start = 0x7b000 }, + { .start = 0x7b004 }, + { .start = 0x7b014 }, + { .start = 0x7b018 }, + { .start = 0x7c000 }, + { .start = 0x7c004 }, + { .start = 0x7c014 }, + { .start = 0x7c018 }, {}, }; @@ -187,7 +187,9 @@ static bool intel_dmc_wl_reg_in_range(i915_reg_t reg, u32 offset = i915_mmio_reg_offset(reg); for (int i = 0; ranges[i].start; i++) { - if (ranges[i].start <= offset && offset <= ranges[i].end) + u32 end = ranges[i].end ?: ranges[i].start; + + if (ranges[i].start <= offset && offset <= end) return true; } -- 2.25.1