RISC-V: Atomic and Locking Code
authorPalmer Dabbelt <palmer@dabbelt.com>
Tue, 11 Jul 2017 01:02:19 +0000 (18:02 -0700)
committerPalmer Dabbelt <palmer@dabbelt.com>
Tue, 26 Sep 2017 22:26:45 +0000 (15:26 -0700)
commitfab957c11efe2f405e08b9f0d080524bc2631428
treef42fd6aca01844c410583cbad08c83a75b387ebf
parent76d2a0493a17d4c8ecc781366850c3c4f8e1a446
RISC-V: Atomic and Locking Code

This contains all the code that directly interfaces with the RISC-V
memory model.  While this code corforms to the current RISC-V ISA
specifications (user 2.2 and priv 1.10), the memory model is somewhat
underspecified in those documents.  There is a working group that hopes
to produce a formal memory model by the end of the year, but my
understanding is that the basic definitions we're relying on here won't
change significantly.

Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
arch/riscv/include/asm/atomic.h [new file with mode: 0644]
arch/riscv/include/asm/barrier.h [new file with mode: 0644]
arch/riscv/include/asm/bitops.h [new file with mode: 0644]
arch/riscv/include/asm/cacheflush.h [new file with mode: 0644]
arch/riscv/include/asm/cmpxchg.h [new file with mode: 0644]
arch/riscv/include/asm/io.h [new file with mode: 0644]
arch/riscv/include/asm/spinlock.h [new file with mode: 0644]
arch/riscv/include/asm/spinlock_types.h [new file with mode: 0644]
arch/riscv/include/asm/tlb.h [new file with mode: 0644]
arch/riscv/include/asm/tlbflush.h [new file with mode: 0644]