drm/i915/display: Compute vrr_vsync params
authorMitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Fri, 22 Mar 2024 03:11:56 +0000 (08:41 +0530)
committerAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Thu, 4 Apr 2024 07:57:06 +0000 (13:27 +0530)
commite8cd188e91bbd0f40761fafcd4c3cce55651685a
tree76fa8176c70b5c5c0cbcd5e2a93ec04932ad831c
parentabe1cd9ab5be1199e47064c9d4ccd45e4ded1d26
drm/i915/display: Compute vrr_vsync params

Compute vrr_vsync_start/end, which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.

--v2:
- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
- Updated bit fields of VRR_VSYNC_START/END. (Ankit)

--v3:
- Add PIPE_CONF_CHECK_I(vrr.vsync_start/end).
- Read/write vrr_vsync params only when we intend to send
adaptive_sync sdp.

--v4:
- Use VRR_SYNC_START/END macros correctly.

--v5:
- Send AS SDP only when VRR is enabled.

--v6:
- Add TRANS_VRR_VSYNC before enabling VRR as per bspec. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240322031157.3823909-9-mitulkumar.ajitkumar.golani@intel.com
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_display_types.h
drivers/gpu/drm/i915/display/intel_vrr.c
drivers/gpu/drm/i915/i915_reg.h