drm/i915: Allow M/N change during fastset on bdw+
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 7 Sep 2022 09:10:55 +0000 (12:10 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 8 Sep 2022 11:21:50 +0000 (14:21 +0300)
commite6f29923c0489b6fec1ac000f2c045df43ec081c
tree39e4f263a4a18e846260bd3539d3db0b3f255e3c
parent74d6f31fa427b87616bc65987a8aff460da1e670
drm/i915: Allow M/N change during fastset on bdw+

On BDW+ M/N are double buffered and so we can easily reprogram them
during a fastset. So for eDP panels that support seamless DRRS we
can just change these without a full modeset.

For earlier platforms we'd need to play tricks with M1/N1 vs.
M2/N2 during the fastset to make sure we do the switch atomically.
Not sure the added complexity is worth the hassle, so leave it
alone for now.

The slight downside is that we have to keep the link running at
a link rate capable of supporting the highest refresh rate we
want to use. For the moment we just pick the highest mode the
panel reports and calculate the link based on that. This might
need further refinement (eg. if we run into bandwidth
restrictions)...

v2: Only use the high link rate if the platform really supports
    the seamless M/N change uring fastset (ie. bdw+)
v3: Rebase due to HAS_DOUBLE_BUFFERED_M_N()

Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-16-ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_display_types.h
drivers/gpu/drm/i915/display/intel_dp.c