irqchip/riscv-aplic: Add support for MSI-mode
authorAnup Patel <apatel@ventanamicro.com>
Thu, 7 Mar 2024 14:03:05 +0000 (19:33 +0530)
committerThomas Gleixner <tglx@linutronix.de>
Mon, 25 Mar 2024 16:38:29 +0000 (17:38 +0100)
commitca8df97fe6798afbe395fc4a8e23bac0c7fbd248
tree69249e22caf0efc1419b39a47b12b68f9c86a567
parent2333df5ae51ead2188d07c99e841e159a664741e
irqchip/riscv-aplic: Add support for MSI-mode

The RISC-V advanced platform-level interrupt controller (APLIC) has
two modes of operation: 1) Direct mode and 2) MSI mode.
(For more details, refer https://github.com/riscv/riscv-aia)

In APLIC MSI-mode, wired interrupts are forwared as message signaled
interrupts (MSIs) to CPUs via IMSIC.

Extend the existing APLIC irqchip driver to support MSI-mode for
RISC-V platforms having both wired interrupts and MSIs.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Link: https://lore.kernel.org/r/20240307140307.646078-8-apatel@ventanamicro.com
drivers/irqchip/Kconfig
drivers/irqchip/Makefile
drivers/irqchip/irq-riscv-aplic-main.c
drivers/irqchip/irq-riscv-aplic-main.h
drivers/irqchip/irq-riscv-aplic-msi.c [new file with mode: 0644]